2.3.2. Back-to-back messaging from Core0 to Core1

In this example system, there are two cores and four mailboxes. Core0 is the source core and Core1 is the destination core. Core0 uses Channel ID1 and Core1 uses Channel ID2, as in Back-to-back messaging from Core0 to Core1. Core0 sends a message to Core1, obtains an acknowledge, and sends another message to Core1, which is also acknowledged. This example assumes that the IPCM is not in integration test mode. Mailboxes 1-3 are inactive and Auto Acknowledge and Auto Link are disabled. Figure 2.7 shows the configuration.

Figure 2.7. Configuration, back-to-back messaging from Core?0 to Core?1

Figure 2.8 shows the messaging sequence.

Figure 2.8. Back-to-back messaging from Core?0 to Core?1

In this example, the following sequence occurs:

  1. Core0 gains control of Mailbox0 and identifies itself as the source core by setting bit 0 in the IPCM0SOURCE Register.

  2. Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the IPCM0MSTATUS Register.

  3. Core0 defines the destination core by setting bit 1 in the IPCM0DSTATUS Register.

  4. Core0 programs the data payload, DA7A0000.

  5. Core0 sets bit 0 of the IPCM0SEND Register to send the interrupt to the destination core.

  6. Core1 reads the IPCMRIS1 Register and reads the data payload.

  7. Core1 optionally updates the data payload for the Acknowledge, DA7A1111.

  8. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the Manual Acknowledge back to Core?0.

  9. Core0 reads the IPCMRIS0 Register and reads the data payload.

  10. Core0 programs the data payload for the next message, DA7A2222.

  11. Core0 clears bit 1 and sets bit 0 of the IPCM0SEND Register to send the interrupt to the destination core.

  12. Core1 reads the IPCMRIS1 Register and reads the data payload.

  13. Core1 optionally updates the data payload for the Acknowledge, DA7A3333.

  14. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the Manual Acknowledge back to Core0.

  15. Core0 reads the IPCMRIS0 Register and reads the data payload.

  16. Core0 clears the interrupt and releases ownership of the mailbox by clearing the IPCM0SOURCE Register, which in turn clears the IPCM0DSTATUS, IPCM0MSTATUS, IPCM0SEND, and IPCM0DR0 Registers.

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