PrimeCell® Inter-Processor Communications Module (PL320) Technical Reference ManualRevision: r0p0
Home > Programmer’s Model > Register descriptions > Mailbox Mask Set Registers

3.3.6. Mailbox Mask Set Registers

The write-only IPCMxMSET Registers set bits in the Mailbox Mask Registers. They can only be written to after the Mailbox Source Register is defined.

Table 3.7 lists the register bit assignments.

Table 3.7. IPCMxMSET Register bit assignments

BitNameFunction
[31:0]Mask SetUsed to set bits in the Mailbox Mask Register
Copyright © 2003, 2004. ARM Limited. All rights reserved.ARM DDI 0306B
Non-Confidential
PDF file icon  PDF version
Home > Programmer’s Model > Register descriptions > Mailbox Mask Set Registers