4.2.1. Integration Test Control Register

The read/write IPCMTCR Register controls the IPCM integration test mode. When ITEN=1, the IPCM is placed in integration test mode. Figure 4.1 shows and Table 4.1 lists the register bit assignments.

Figure 4.1. IPCMTCR Register bit assignments

Table 4.1. IPCMTCR Register bit assignments

BitNameFunction
[31:1]-Read undefined. Write as zero.
[0]ITENIntegration test enable: 0 = integration test mode disabled 1 = integration test mode enabled.
Copyright © 2003, 2004. ARM Limited. All rights reserved.ARM DDI 0306B
Non-Confidential