A.1. AMBA AHB signals

Table A.1 lists the AMBA AHB common signals.

Table A.1. AMBA AHB common signals

NameTypeSource/destinationDescription
HCLKInputClock controllerClock input for all IPCM flops
HRESETnInputReset controllerAHB bus reset, active LOW

Table A.2 lists the AMBA AHB slave signals.

Table A.2. AMBA AHB slave signals

NameTypeSource/destinationDescription
HADDR[11:2]InputSend or receive core AHBSystem address bus
HRDATA[31:0]OutputSend or receive core AHBRead data bus
HREADYInputSend or receive core AHBTransfer completed input. When HIGH, this signal indicates that a transfer has finished on the bus.
HREADYOUTOutputSend or receive core AHBTransfer done output. When HIGH, this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. The IPCM is always zero wait state, therefore this signal is always driven HIGH.
HRESP[1:0]OutputSend or receive core AHBThe transfer response provides additional information on the status of a transfer. The IPCM always provides an OKAY response.
HSELInputSend or receive core AHBSlave select signal for IPCM control and status registers
HSIZE[2:0]InputSend or receive core AHBTransfer size signal. This signal indicates the size of the current transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit). The IPCM only supports 32-bit transfers.
HTRANSInputSend or receive core AHBIndicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. The IPCM only uses HTRANS[1].
HWDATA[31:0]InputSend or receive core AHBWrite data bus
HWRITEInputSend or receive core AHBTransfer direction signal. When HIGH, this signal indicates a write and, when LOW, a read
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