3.3.15. PrimeCell Identification Registers

The IPCMPCellID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. You can conceptually treat the registers as a single 32-bit register. The register is used as a standard cross-peripheral identification system.

Figure 3.9 shows the register bit assignments.

Figure 3.9. PrimeCell Identification Register bit assignments

The four PrimeCell Identification Registers are described in the following subsections:

PrimeCell Identification Register 0

The hard-coded IPCMPCellID0 Register defines the reset value. Table 3.19 lists the bit assignments for the IPCMPCellID0 Register.

Table 3.19. IPCMPCellID0 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

IPCMPCellID0

These bits read back as 0x0D

PrimeCell Identification Register 1

The hard-coded IPCMPCellID1 Register defines the reset value. Table 3.20 lists the bit assignments for the IPCMPCellID1 Register.

Table 3.20. IPCMPCellID1 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

IPCMPCellID1

These bits read back as 0xF0

PrimeCell Identification Register 2

The hard-coded IPCMPCellID2 Register defines the reset value. Table 3.21 lists the bit assignments for the IPCMPCellID2 Register.

Table 3.21. IPCMPCellID2 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

IPCMPCellID2

These bits read back as 0x05

PrimeCell Identification Register 3

The hard-coded IPCMPCellID3 Register defines the reset value. Table 3.22 lists the bit assignments for the IPCMPCellID3 Register.

Table 3.22. IPCMPCellID3 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

IPCMPCellID3

These bits read back as 0xB1

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