ARM968E-S™ Technical Reference Manual A.5.2. ITCM interface signals

Table A.5 shows the ARM968E-S ITCM interface signals.

Table A.5. ITCM interface signals

Signal	Direction	Function
ITCMADDR[21:2]	Output	ITCM address. Addresses up to 4MB. Output delay 90% of clock cycle.
ITCMWD[31:0]	Output	ITCM write data.
ITCMCS	Output	ITCM chip select.
ITCMWE[3:0]	Output	ITCM byte write enable. Each bit indicates a write to RAM of the corresponding byte in ITCMWD[31:0]. For example: b0000 = No write. b0001 = Byte write of the least significant byte. b1000 = Byte write of the most significant byte. b0011 = A half-word write of the least significant two bytes. ITCMWE[3:0] bits are set only when a write is taking place, so when ITCMnRW is not set, ITCMWE[3:0] = b0000.
ITCMnRW	Output	ITCM read/write: 1 = write access 0 = read access.
ITCMRD[31:0]	Input	Instruction TCM read data.
ITCMWAIT	Input	ITCM wait. If HIGH, ITCM cannot service any requests in next cycle. Stall the processor for multiple-cycle-access RAM on ITCM interface. Used to stall the processor for DMA access to single-port ITCM.
ITCMSIZE[4:0]	Input	ITCM size: b00000 = 0B b00001 = 1KB b00010 = 2KB b00011 = 4KB b00100 = 8KB b00101 = 16KB b00110 = 32KB	b00111 = 64KB b01000 = 128KB b01001 = 256KB b01010 = 512KB b01011 = 1MB b01100 = 2MB b01101 = 4MB.
		The supported sizes are 0 and 2ⁿKB for n = 0-12.
ITCMERROR	Input	ITCM error signal. Enables the processor to read error conditions during read accesses.

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