The ARM968E-S processor uses a single rising-edge clock signal, CLK, to time all internal activity. In a system with an embedded processor, it can be best to run the AHB at a lower clock rate. To support a lower AHB clock rate, the processor must have a clock enable, HCLKEN, to time AHB transfers.

The HCLKEN input is driven HIGH around a rising edge of CLK to indicate that this rising edge is also a rising edge of HCLK. HCLK must therefore be synchronous to CLK.

When the processor is running from TCM or performing writes using the AHB write buffer, the HCLKEN and HREADY inputs are decoupled from the SYSCLKEN stall signal. The processor is stalled only by TCM stall cycles or if the write buffer overflows. This means that the processor is executing instructions at the faster CLK rate and is decoupled from the HCLK domain AHB system.

If however, an AHB read or unbuffered write is required, the processor stalls until the AHB transfer is complete. Because the AHB system is being clocked by the slower HCLK, the processor must examine HCLKEN to detect when to drive out the AHB address and control signals to start an AHB transfer. HCLKEN then has to detect the following rising edges of HCLK so that the BIU can detect when the access completes. Figure 5.7 shows an example of an AHB read with a 3:1 ratio of CLK to HCLK.

If the slave being accessed at the HCLK rate has a multicycle response, the HREADY input to the processor is driven LOW until the data is ready to be returned. The BIU must therefore perform a logical AND of the HREADY response and HCLKEN to detect that the AHB transfer has completed. When the AND is true, the processor is then enabled by reasserting SYSCLKEN.