ARM968E-S ™ TechnicalReference Manual

Revision: r0p1


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the ARM968E-S processor
Feedback on this manual
1. Introduction
1.1. About the ARM968E-S processor
1.2. TCM access
1.2.1. BIU AHB-Lite master interface
1.2.2. DMA AHB-Lite slave interface
1.3. Debug interface configurations
1.3.1. Reduced debug interface
1.3.2. Full debug interface
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor states
2.2.1. Switching state
2.2.2. Switching state during exception handling
2.3. Processor operating modes
2.4. Registers
2.4.1. Accessing the register set in Thumb state
2.4.2. Program Status Registers
2.5. Data types
2.6. Memory formats
2.7. Exceptions
2.7.1. Entering an exception
2.7.2. Exiting an exception
2.7.3. Exception vectors
2.7.4. Exception priorities
3. Memory Map
3.1. About the ARM968E-S memory map
3.2. Tightly-coupled memory address space
3.3. Bufferable write address space
4. System Control Coprocessor
4.1. About the System Control Processor
4.2. Accessing CP15 registers
4.3. CP15 register summary
4.4. CP15 register descriptions
4.4.1. CP15 c0 Device ID Register
4.4.2. CP15 c0 TCM Size Register
4.4.3. CP15 c1 Control Register
4.4.4. CP15 c7 core control operations
4.4.5. CP15 c13 Trace Process ID Register
4.4.6. CP15 c15 Configuration Control Register
4.5. CP15 instruction summary
5. Bus Interface Unit
5.1. About the BIU
5.2. Bus transfer characteristics
5.2.1. Transfer size
5.2.2. Sequential and nonsequential transfers
5.2.3. BIU protection control
5.2.4. BIU locked transfers
5.3. Instruction prefetch buffer
5.3.1. Optimized Thumb instruction prefetch
5.3.2. IPB disable bit
5.3.3. AHB error response in IPB
5.3.4. IPB timing examples
5.4. AHB write buffer
5.4.1. Committing write data to the AHB write buffer
5.4.2. Draining write data from the AHB write buffer
5.4.3. Enabling the AHB write buffer
5.4.4. Disabling the AHB write buffer
5.5. AHB bus master interface
5.5.1. Overview of AHB
5.6. AHB transfer descriptions
5.6.1. Back-to-back data transfers
5.6.2. Data burst support
5.7. AHB clocking
5.8. CLK-to-HCLK skew
5.8.1. Clock tree insertion at top level
5.8.2. Hierarchical clock tree insertion
6. Tightly-Coupled Memory Interface
6.1. About the TCM interface
6.2. Enabling TCM
6.2.1. Using INITRAM input pin
6.2.2. Using CP15 c1 Control Register
6.3. TCM write buffers
6.3.1. Forcing strict read/write ordering
6.4. TCM size
6.5. TCM error detection signals
6.6. Interface timing
6.6.1. TCM reads with zero wait states
6.6.2. TCM reads with one wait state
6.6.3. TCM reads with four wait states
6.6.4. TCM writes with zero wait states
6.6.5. TCM write with one wait state
6.6.6. TCM write with two wait states
6.6.7. TCM accesses with varying TCM waitstates
6.6.8. Speculative TCM read access
6.7. TCM implementation examples
6.7.1. Simplest zero-wait-state RAM example
6.7.2. Byte-banks of RAM examples
6.7.3. Multiple banks of RAM example
6.7.4. Sequential RAM example
6.7.5. Single or multiple wait-state RAMexample
7. DMA Interface
7.1. About the DMA interface
7.2. Bus transfer characteristics
7.2.1. Transfer size
7.2.2. Sequential and nonsequential transfers
7.2.3. Burst types
7.2.4. Protection control
7.2.5. Error response limitations
7.3. AHB bus slave interface
7.4. Wait-for-interrupt mode
7.5. AHB transfer descriptions
7.5.1. DMA reads
7.5.2. DMA read with error response
7.5.3. DMA read with wait state
7.5.4. DMA write with wait state
7.5.5. Interleaved DMA writes to DTCM
8. Debug Support
8.1. About the debug interface
8.1.1. Entering debug state
8.1.2. Clocks
8.2. Debug systems
8.2.1. Debug host
8.2.2. Protocol converter
8.2.3. ARM968E-S debug target
8.3. Debug data chain 15
8.4. Debug interface signals
8.4.1. Entry into debug state on breakpoint
8.4.2. Breakpoints and exceptions
8.4.3. Watchpoints
8.4.4. Watchpoints and exceptions
8.4.5. Debug request
8.4.6. Actions of the ARM9E-S core in debug state
8.5. ARM9E-S core clock domains
8.6. Determining the core and system state
8.7. About the EmbeddedICE-RT
8.8. Disabling EmbeddedICE-RT
8.9. The debug comms channel
8.9.1. Debug comms channel registers
8.9.2. Communications using the debug comms channel
8.10. Monitor debug-mode
8.11. Additional debug reading
9. Embedded Trace Macrocell Interface
9.1. About the ETM interface
9.2. Enabling the ETM interface
9.3. Trace support features
9.3.1. FIFOFULL
9.3.2. Configuration Control Register
9.3.3. Trace Process ID Register
10. Test Support
10.1. About the ARM968E-S test methodology
10.2. Scan insertion and ATPG
10.2.1. ARM968E-S test wrapper
11. DFT Interface
11.1. About the DFT interface
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. AHB interface signals
A.3. DMA interface signals
A.4. Debug signals
A.5. TCM interface signals
A.5.1. DTCM0 and DTCM1 interface signals
A.5.2. ITCM interface signals
A.6. ETM interface signals
A.7. DFT interface signals
A.8. Miscellaneous interface signals
B. AC Parameters
B.1. About AC timing parameters
B.2. CLK, HCLKEN, and HRESETn timing parameters
B.3. AHB bus master timing parameters
B.4. DMA interface timing parameters
B.5. Debug interface timing parameters
B.6. JTAG interface timing parameters
B.7. Configuration and exception timingparameters
B.8. INTEST wrapper timing parameters
B.9. ETM interface timing parameters
B.10. TCM interface timing parameters
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM968E-S processor block diagram
2.1. ARM968E-S registerset
2.2. Program Status Registers
2.3. Little-endian and big-endian memoryformats
3.1. ARM968E-S memory map
3.2. ITCM aliasing example
4.1. CP15 MCR and MRC instruction format
4.2. Device ID Register
4.3. TCM Size Register
4.4. Control Register
4.5. Trace Process ID Register
4.6. Configuration Control Register
5.1. Nonsequential instruction fetch
5.2. Nonsequential instruction fetch aftera data access
5.3. Back-to-back writes followed by aread
5.4. Single STM followed by sequentialinstruction fetch
5.5. Data burst crossing a 1KB boundary
5.6. SWP instruction
5.7. AHB 3:1 clocking example
5.8. CLK to HCLK sampling
6.1. TCM interface
6.2. TCM reads with zero wait states
6.3. TCM reads with one wait state
6.4. TCM reads with four wait states
6.5. TCM writes with zero wait states
6.6. TCM write with one wait state
6.7. TCM writes with two wait states
6.8. TCM reads and writes with wait statesof varying length
6.9. Simplest zero wait state RAM example
6.10. Byte-banks of RAM example
6.11. Alternative byte-banks of RAM example
6.12. Multiple banks of RAM example
6.13. Sequential RAM example
6.14. Single or multiple wait-state RAMexample
7.1. DMA interface
7.2. Deassertion of STANDBYWFI after anIRQ interrupt
7.3. DMA reads of ITCM
7.4. DMA read of ITCM with error response
7.5. DMA read of ITCM with wait state
7.6. DMA write of DTCM with wait state
7.7. Interleaved DMA writes to DTCM
8.1. Clock synchronization
8.2. Typical debug system
8.3. Block diagram of the ARM9E-S debugmodel
8.4. Breakpoint timing
8.5. Watchpoint entry with data processinginstruction
8.6. Watchpoint entry with branch
8.7. EmbeddedICE-RT interface
8.8. Debug Comms Channel Status Register
8.9. Debug Comms Channel Monitor Debug-ModeStatus Register
9.1. ETM interface
B.1. CLK, HCLKEN, and HRESETn timing parameters
B.2. AHB bus master timing parameters
B.3. DMA interface timing parameters
B.4. Debug interface timing parameters
B.5. JTAG interface timing parameters
B.6. Configuration and exception timingparameters
B.7. INTEST wrapper timing parameters
B.8. ETM interface timing parameters
B.9. TCM interface timing parameters

List of Tables

1.1. Location of block descriptions
2.1. Banked register mode identifiers
2.2. Program Status Register encoding
2.3. Exception return points
2.4. Exception vectors
2.5. Exception priorities
4.1. CP15 register summary
4.2. Encoding of the Device ID Register
4.3. Encoding of the TCM Size Register
4.4. Control Register instructions
4.5. Encoding of the Control Register
4.6. Core control instructions
4.7. Trace Process ID Register instructions
4.8. Configuration Control Register instructions
4.9. Encoding of the Configuration Control Register
4.10. CP15 instruction summary
5.1. BIU transfer characteristics
6.1. Supported TCM RAM sizes
7.1. DMA transfer characteristics
7.2. Active byte lanes with a 32-bit big-endian data bus
7.3. Active byte lanes with a 32-bit big-endian data bus
8.1. Debug data chain 15 bit order
8.2. Mapping of debug data chain 15 address field to CP15 registers
8.3. Debug comms channel registers
8.4. Debug Comms Channel Status Register Encoding
8.5. Debug Comms Channel Monitor Debug-Mode Status Register instructions
8.6. Debug Comms Channel Monitor Debug-Mode Status Register Encoding
A.1. AHB interface signals
A.2. DMA interface signals
A.3. Debug signals
A.4. DTCM0 and DTCM1 interface signals
A.5. ITCM interface signals
A.6. ETM interface signals
A.7. DFT signals
A.8. Miscellaneous interface signals
B.1. CLK, HCLKEN, and HRESETn timing parameters
B.2. AHB bus master timing parameters
B.3. DMA interface timing parameters
B.4. Debug interface timing parameters
B.5. JTAG interface timing parameters
B.6. Configuration and exception timing parameters
B.7. INTEST wrapper timing parameters
B.8. ETM interface timing parameters
B.9. TCM interface timing parameters

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 30January 2004 First r0p0 release
Revision B 10March 2004 Second release with TCM access clarification
Revision C 04November 2004 Third release with corrections ofaddress bus widths in Figures 6-11, 6-12, and 6-13
Revision D 08November 2006 Updated for r0p1. Maintenance release.
Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0311D
Non-Confidential