A.10. CoreSight ITM signals

Table A.10 shows the CoreSight Instrumentation Trace Macrocell (ITM) signals.

Table A.10. CoreSight ITM signals

NameTypeDescriptionClock domain
AFREADYMOutputATB flush acknowledge ATCLK
ATCLKInputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAM[7:0]OutputATB Data - ITMATCLK
ATIDM[6:0]OutputITM IDATCLK
ATREADYMInputATB Ready - ITMATCLK
ATRESETnInputATB resetATCLK
ATVALIDMOutputATB Valid - ITMATCLK
DBGENInputInvasive Debug Enable None
NIDENInputNon-Invasive Debug EnableNone
PADDRDBG[11:2]InputAPB addressPCLKDBG
PADDRDBG31InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBGInputAPB clockN/A
PCLKENDBGInputAPB clock enablePCLKDBG
PENABLEDBGInputAPB enablePCLKDBG
PRDATADBG[31:0]OutputAPB read dataPCLKDBG
PREADYDBGOutputAPB readyPCLKDBG
PRESETDBGnInputAPB resetPCLKDBG
PSELDBGInputAPB selectPCLKDBG
PWDATADBG[31:0]InputAPB write dataPCLKDBG
PWRITEDBGInputAPB writePCLKDBG
SEInputScan enableNone
SPIDENInputSecure Invasive Debug EnableNone
SPNIDENInputSecure Non-Invasive Debug EnableNone
TRIGOUTOutputIndicates a trigger event ATCLK
TRIGOUTACKInputTRIGOUT acknowledgement ATCLK

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