A.9. CoreSight SWO signals

Table A.9 shows the CoreSight Serial Wire Output (SWO) signals.

Table A.9. CoreSight SWO signals

NameTypeDescriptionClock domain
ATCLKInputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAS[7:0]InputATB dataATCLK
ATREADYSOutputATB ready signalATCLK
ATRESETnInputATB asychronous reset active lowATCLK
ATVALIDSInputATB valid signalATCLK
PADDRDBG[11:2]InputAPB address busPCLKDBG
PADDRDBG31InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBGInputAPB clockN/A
PCLKENDBGInputAPB clock enablePCLKDBG
PENABLEDBGInputAPB enablePCLKDBG
PRDATADBG[31:0]OutputAPB read data busPCLKDBG
PREADYDBGOutputAPB ready acknowledgementPCLKDBG
PRESETDBGnInputAPB asychronous reset active lowPCLKDBG
PSELDBGInputAPB slave selectPCLKDBG
PWDATADBG[31:0]InputAPB write data busPCLKDBG
PWRITEDBGInputAPB write or readPCLKDBG
SEInputScan enableNone
TRACECLKINInputTRACEIN clockN/A
TRACESWOOutputSerial wire outputTRACECLKIN
TRESETnInputTRACECLKIN asychronous reset active LOWTRACECLKIN

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential