2.1. About the Debug Access Port

The Debug Access Port (DAP) is an implementation of an ARM Debug Interface version 5.1 (ADIv5.1) comprising a number of components supplied in a single configuration. All the supplied components fit into the various architectural components for Debug Ports (DPs), which are used to access the DAP from an external debugger and Access Ports (APs), to access on-chip system resources.

The debug port and access ports together are referred to as the DAP.

The DAP provides real-time access for the debugger without halting the processor to:

The DAP also provides debugger access to JTAG scan chains of system components, for example non-CoreSight compliant processors. Figure 2.1 shows the top-level view of the functional blocks of the DAP. Figure 2.2, Figure 2.3, and Figure 2.4 show separate components in more detail.

Figure 2.1. Structure of the CoreSight DAP components

Figure 2.2. SWJ Debug Port

Figure 2.3. AHB Access Port

Figure 2.4. APB Access Port

The DAP enables debug access to the complete SoC using a number of master ports. Access to the CoreSight Debug Advanced Peripheral Bus (APB) is enabled through the APB Access Port (APB-AP) and APB Multiplexor (APB-MUX), and system access through the Advanced High-performance Bus Access Port (AHB-AP).

The DAP comprises the following interface blocks:

The debug port supplied with the DAP is:

Serial Wire and JTAG Debug Port (SWJ-DP)

This is a combined debug port which can communicate in either JTAG or Serial Wire protocols as defined in ADIv5.1. It contains two debug ports, the SW-DP and the JTAG-DP that you can select through an interface sequence to move between debug port interfaces.

The JTAG-DP is compliant with DP architecture version 0. The SW-DP is compliant with DP architecture version 2 and Serial Wire protocol version 2, which enable an SW-DP to share a target connection with other SW-DPs or other components implementing different protocols.

The access ports specified for CoreSight are:

AHB Access Port (AHB-AP)

The AHB-AP provides an AHB-Lite master for access to a system AHB bus. This is compliant with the Memory Access Port (MEM-AP) in ADIv5.1 and can perform 8 to 32-bit accesses.

APB Access Port (APB-AP)

The APB-AP provides an APB master in AMBA v3.0 for access to the Debug APB bus. This is compliant with the MEM-AP with a fixed transfer size of 32-bits.

JTAG Access Port (JTAG-AP)

The JTAG-AP provides JTAG access to on-chip components, operating as a JTAG master port to drive JTAG chains throughout the ASIC. This is an implementation of the JTAG-AP in ADIv5.1.

The DAP also implements a DAPBUS interface to enable an additional access port to be connected externally for connection to certain processors.

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