4.4.13. External Multiplexor Control Register, ASICCTL, 0x144

Figure 4.16 shows the bit assignments for the External Multiplexor Control Register.

Figure 4.16. External Multiplexor Control Register bit assignments


Table 4.14 shows the bit assignments for the External Multiplexor Control Register.

Table 4.14. External Multiplexor Control Register bit assignments

BitsNameDescription
[31:8]-Reserved RAZ DNM.
[7:0] ASICCTL

Implementation-defined ASIC control, value written to the register is output on ASICCTL[7:0].

If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the Device ID Register. This is done within a Verilog define EXTMUXNUM. See ECT CoreSight defined registers.


Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential