7.3.1. CSTF Control Register, 0x000

The CSTF Control Register enables the slave ports and defines the hold time of the slave ports. Hold time refers to the number of transactions that are output on the funnel master port from the same slave while that slave port ATVALIDSx is HIGH. Hold time does not refer to clock cycles in this context. Figure 7.2 shows the bit assignments.

Figure 7.2. CSTF Control Register bit assignments

Table 7.2 shows the bit assignments.

Table 7.2. CSTF Control Register bit assignments

BitsField nameDescription
[31:12]-Reserved SBZ
[11:8]Minimum hold time[3:0]

The formatting scheme can easily become inefficient if fast switching occurs, so, where possible, this must be minimized. If a source has nothing to transmit, then another source is selected irrespective of the minimum number of cycles. Reset is 0x3. The CSTF holds for the minimum hold time and one additional cycle.

The maximum value that can be entered is 0xE and this equates to 15 cycles.

0xF is reserved.

[7]Enable Slave port 7

Setting this bit enables this input, or slave, port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. The reset value is all clear, that is, all ports disabled.

[6]Enable Slave port 6
[5]Enable Slave port 5
[4]Enable Slave port 4
[3]Enable Slave port 3
[2]Enable Slave port 2
[1]Enable Slave port 1
[0]Enable Slave port 0

See the Data Overhead section in the CoreSight System Design Guide for more information.

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