8.5. TPIU CoreSight management registers

The information given here is specific to the TPIU:

Claim tags, 0xFA0 and 0xFA4

The TPIU implements a four-bit claim tag. The use of bits [3:0] is software defined.

Lock access mechanism, 0xFB0 and 0xFB4

The TPIU implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked.

Authentication Status Register, 0xFB8

Reports the required security level. The TPIU has a default value of 0x00 to indicate that this functionality is not implemented.

Device ID, 0xFC8

The TPIU has a default value of 0x0A0.

Table 8.4 shows the Device ID bit values.

Table 8.4. Device ID bit values

BitsValueDescription
[31:12]0x00000Reserved.
[11]0Indicates Serial Wire Output (UART/NRZ) is not supported.
[10]0Indicates Serial Wire Output (Manchester) is not supported.
[9]0Indicates trace clock + data is supported.
[8:6]3’b010FIFO size in powers of 2. A value of 2 gives a FIFO size of 4 entries, 16 bytes.
[5]1’b1Indicates the relationship between ATCLK and TRACECLKIN. 0x1 indicates asynchronous.
[4:0]5’b0000

Hidden Level of Input multiplexing.

When nonzero this value indicates the type/number of ATB multiplexing present on the input to the ATB. Currently only 0x00 is supported, that is, no multiplexing present.

This value is used to assist topology detection of the ATB structure.


Device Type Identifier, 0xFCC

0x11 indicates this device is a trace sink (0x1) and specifically a TPIU (0x1).

Part number, 0xFE4[3:0], 0xFE0[7:4], and 0xFE0[3:0]

Upper, middle, and lower BCD value of Device number. This is set to 0x912.

Designer JEP106 value, 0xFD0[3:0], 0xFE8[2:0], 0xFE4[7:4]

The TPIU is identified as an ARM component with a JEP106 identity at 0x3B and a JEP106 continuation code at 0x4 (fifth bank).

Component class, 0xFF4[7:4]

The TPIU complies to the CoreSight class of components and this value is set to 0x9.

See Table 1.1 for the current value of the revision field at offset 0xFE8[7:4].

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