9.3.6. ETB Trigger Counter Register, TRG, 0x01C

The Trigger Counter Register disables write access to the Trace RAM by stopping the Formatter after a defined number of words have been stored following the trigger event. The number of 32-bit words written into the Trace RAM following the trigger event is equal to the value stored in this register+1.

Table 9.10 shows the ETB Trigger Counter Register bit assignments.

Table 9.10. ETB Trigger Counter Register bit assignments.

BitsTypeNameFunction
[31:CSETB_ADDR_WIDTH]--

Reserved.

CSETB_ADDR_WIDTH defines the address bus width, and the RAM depth supported

[CSETB_ADDR_WIDTH-1:0]R/WTrigger Counter, TRG

Trigger Counter Register.

The counter is used as follows:

  • Trace after

    The counter is set to a large value, slightly less than the number of entries in the RAM.

  • Trace before

    The counter is set to a small value.

  • Trace about

    The counter is set to half the depth of the Trace RAM.

This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the register is not updated. A read access is permitted with trace capture enabled.


Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential