8.6.12. TPIU Integration Test Registers

Integration Test Registers are provided to simplify the process of verifying the integration of the TPIU with other devices in a CoreSight system. These registers enable direct control of outputs and the ability to read the value of inputs. You must only use these registers when the Integration Mode Control Register (0xF00) bit [0] is set to 1.

The registers in the TPIU enable the system to set the FLUSHINACK and TRIGINACK output pins. The FLUSHIN and TRIGIN inputs to the TPIU can also be read. The other Integration Test Registers are for testing the integration of the ATB slave interface on the TPIU. For details of how to use these signals see the applicable CoreSight DK Integration Manual.

This section describes the following registers:

Integration Test Trigger In and Flush In Acknowledge Register, ITTRFLINACK, 0xEE4

The Integration Test Trigger In and Flush In Acknowledge Register enables control of the TRIGINACK and FLUSHINACK outputs from the TPIU. Figure 8.11 shows the bit assignments.

Figure 8.11. Integration Test Trigger In and Flush In Acknowledge Register bit assignments


Table 8.13 shows the bit assignments.

Table 8.13. Integration Test Trigger In and Flush In Acknowledge Register bit assignments

BitsTypeNameDescription
[31:2] --Reserved
[1]WOFLUSHINACKSet the value of FLUSHINACK
[0]WOTRIGINACKSet the value of TRIGINACK

Integration Test Trigger In and Flush In Register, ITTRFLIN, 0xEE8

The Integration Test Trigger In and Flush In Register contains the values of the FLUSHIN and TRIGIN inputs to the TPIU. Figure 8.12 shows the bit assignments.

Figure 8.12. Integration Test Trigger In and Flush In Register bit assignments


Table 8.14 shows the bit assignments.

Table 8.14. Integration Test Trigger In and Flush In Register bit assignments

BitsTypeNameDescription
[31:2] --Reserved RAZ/SBZP
[1]ROFLUSHINRead the value of FLUSHIN
[0]ROTRIGINRead the value of TRIGIN

Integration Test ATB Data Register 0, ITATBDATA0, 0xEEC

The Integration Test ATB Data Register 0 contains the value of the ATDATAS inputs to the TPIU. The values are only valid when ATVALIDS is HIGH. Figure 8.13 shows the bit assignments.

Figure 8.13. Integration Test ATB Data Register 0 bit assignments


Table 8.15 shows the bit assignments.

Table 8.15. Integration Test ATB Data Register 0 bit assignments

BitsTypeNameDescription
[31:5] --Reserved
[4]ROATDATA[31]Read the value of ATDATAS[31]
[3]ROATDATA[23]Read the value of ATDATAS[23]
[2]ROATDATA[15]Read the value of ATDATAS[15]
[1]ROATDATA[7]Read the value of ATDATAS[7]
[0]ROATDATA[0]Read the value of ATDATAS[0]

Integration Test ATB Control Register 2, ITATBCTR2, 0xEF0

The Integration Test ATB Control Register 2 enables control of the ATREADYS and AFVALIDS outputs of the TPIU. Figure 8.14 shows the bit assignments.

Figure 8.14. Integration Test ATB Control Register 2 bit assignments


Table 8.16 shows the bit assignments.

Table 8.16. Integration Test ATB Control Register 2 bit assignments

BitsTypeNameDescription
[31:2] --Reserved
[1]WOAFVALIDSet the value of AFVALIDS
[0]WOATREADYSet the value of ATREADYS

Integration Test ATB Control Register 1, ITATBCTR1, 0xEF4

The Integration Test ATB Control Register 1 contains the value of the ATIDS input to the TPIU. This is only valid when ATVALIDS is HIGH. Figure 8.15 shows the bit assignments.

Figure 8.15. Integration Test ATB Control Register 1 bit assignments


Table 8.17 shows the bit assignments.

Table 8.17. Integration Test ATB Control Register 1 bit assignments

BitsTypeNameDescription
[31:7] --Reserved RAZ/SBZP
[6:0]ROATIDRead the value of ATIDS

Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8

The Integration Test ATB Control Register 0 captures the values of the ATVALIDS, AFREADYS, and ATBYTESS inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of ATBYTESS is only valid when ATVALIDS, bit [0], is HIGH. Figure 8.16 shows the bit assignments.

Figure 8.16. Integration Test ATB Control Register 0 bit assignments


Table 8.18 shows the bit assignments.

Table 8.18. Integration Test ATB Control Register 0 bit assignments

BitsTypeNameDescription
[31:10]--Reserved RAZ/SBZP
[9:8]ROATBYTESRead the value of ATBYTESS
[7:2] --Reserved RAZ/SBZP
[1]ROAFREADYRead the value of AFREADYS
[0]ROATVALIDRead the value of ATVALIDS

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