12.5. Stimulus registers

Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated.

The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. See SWIT packet.

The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.


Any instrumented secure code must use the upper 16 (16-31) register locations that are masked against secure non-invasive enable. You must enable both secure and non-secure transactions to the ITM.

The APB interface does not provide an atomic Read Modify Write (RMW), so an exclusive monitor must be used if a polled printf is used concurrently with ITM usage by interrupts or other threads. The following polled code guarantees stimulus is not lost by polled access to the ITM:

    ; R0 = FIFO-full/exclusive status
    ; R1 = base of ITM stimulus ports
    ; R2 = value to write
    LDREX R0,[R1,#??]    ; read FIFO status and request excl lock
    CZBEQ R0,retry       ; FIFO not ready, try again
    STREX R0,R2,[R1,#??] ; store if FIFO !Full and excl lock
    CZBNE R0,retry       ; excl lock failed, try again

If multiple writes are performed to the ITM when the FIFO is full, the transaction is discarded although no error or stall is generated on the interface.

These registers are not blocked by the Lock Access Register.

Writes to registers to 0x080-0xDFC result in no SWIT packet being transmitted. Reads from these registers return a 0x0. This address space is reserved for future stimulus registers.


The DEVID specifies how many stimulus registers are implemented.

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