12.1.2. Timestamp packet

Timestamp packets encode timestamp information, generic control, and synchronization. The compression scheme uses delta timestamps. Emitting a timestamp zeroes the time counter. Timestamp resolution is related to the clock on the ATB interface. To prevent overflow, the timestamp is emitted at 95% of the counter limit.

The CoreSight ITM implementation has a 21-bit counter, emitting up to TS[20:0], and emitting a full timestamp at 2,000,000 (21'h1E847F) cycles. The architecture allows for a 28-bit counter.

Figure 12.4 shows the layout of an timestamp packet.

Figure 12.4. Timestamp packet layout

In Figure 12.4:


Continuation bit, a byte follows.

Leading zeroes are implied where C=0, to compress the timestamp packet into the minimum of bytes.

TS [27:0]

Byte packing timestamp information.


Timestamp control where:

Only one byte output (header only) (C == 0 of Byte 0)

Single byte timestamps are optimized encodings for when there is a timestamp of value 1-6 with no skew.

[b000] = Reserved timestamp control.

[b001-b110] = Timestamp emitted synchronous to ITM data.

[b111] = Overflow ITM.

Two+ bytes (header + payload) (C == 1 of Byte 0)

[b000-b011] = Reserved timestamp control.

[b100] = Timestamp emitted synchronous to ITM data.

[b101] = Timestamp emitted delayed to ITM.

[b110] = Packet emitted delayed.

[b111] = Packet and timestamp emitted delayed.

For example, a timestamp value of 7 is transmitted as two bytes. The value of 7 is transmitted in the second byte and delay information in the first byte.

A packet delay marker is emitted when ITM attempts to write to the FIFO but are blocked because of a priority rule, or the FIFO not accepting the data.

A timestamp delay marker is emitted when a timestamp is ready but the FIFO is unable to accept the packet. A delay is not marked if waiting on higher priority transactions, because the timestamp continues to count.

The timestamp counter zeroes on a successful write. Timestamps are appended after the source, SWIT. The exception is if a synchronization packet is transmitted after the SWIT or the timestamp counter has overflowed, so the timestamp is preceded by an OVERFLOW or if a full timestamp reference, two million, is reached and a packet is emitted.

For example, a timestamp is configured to count every ATB clock, with a value of 1001 on the first ITM packet:

1000    idle
1001    SWIT
1002    fifo not ready
1003    fifo not ready
1004    TS=1004 with TS delay marked (3 Bytes 0xd0, 0xec, 0x07)
0       SWIT
1       SWIT
2       TS=2 (single byte 0x20)
0       SWIT
1          fifo not ready / ITM packet presented but not accepted
2          SWIT
3          TS=3 packet delay marked (2 Bytes 0xe0, 0x03)
0          idle
1          idle
2          idle
1999997    idle
1999998    idle
1999999    TS=1999999 (2,000,000 ticks)
0          idle
1          idle
2097146    fifo not ready
2097147    fifo not ready / ITM packet presented but not accepted
2097148    SWIT packet
2097149    fifo not ready
2097150    fifo not ready
2097151    fifo not ready (2^21 limit)
0          fifo not ready
1          fifo not ready
2          fifo not ready
3          OVERFLOW marked on TS, TS=3, packet delay marked, TS delay marked
           (3 Bytes 0x70, 0xF0, 0x03)
0          fifo not ready
1          fifo not ready

SWIT packet

Instrumentation trace originates from a software application writing to stimulus ports of ITM. Figure 12.5 shows the layout of an overflow packet.

Figure 12.5. SWIT packet layout

In Figure 12.5:

  • S[1:0] = Payload size. b01=8, b10=16, b11=32, b00=invalid

  • B[4:0] = 5 bits of address, PADDRDBG[7:2]

  • Payload[31:0] = Data written from application.

Reserved encodings

Reserved encodings, at packet b0100, are not implemented in the ITM.

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