2.7.1. External interfaces

The primary external interface to the system is an AHB-Lite master port supporting the following:

The AHB-Lite master port does not support the following:

Table 2.17 shows the other AHB-AP ports.

Table 2.17. Other AHB-AP ports

DBGENInputEnables AHB-AP transfers if HIGH. Access to the AHB-AP registers is still permitted if DBGEN is LOW, but no AHB transfers are initiated. If a transfer is attempted when DBGEN is LOW, then the DAP bus returns DAPSLVERR HIGH.
SPIDENInputPermits secure transfers to take place on the AHB-AP. If SPIDEN is HIGH, then HPROT[6] can be asserted as programmed into the SProt bit in the Control/Status Word Register. See AHB-AP Control/Status Word Register, CSW, 0x00.
nCDBGPWRDNInputIndicates that the debug infrastructure is powered down and enables clamping of signals driven onto the system AHB interface, and clamping of inputs to the debug domain.
nCSOCPWRDNInputIndicates that the system AHB interface is powered down. Ensures no transfers can be initiated and forces an error response to be generated in the access port. It also clamps inputs to the system domain.

HPROT encodings

HPROT[6:0] is provided as an external port and is programmed from the Prot field in the CSW register with the following conditions:

  • HPROT[4:0] programming is supported

  • HPROT[5] is not programmable and always set LOW. Exclusive access is not supported, and so HRESP[2] is not supported

  • HPROT[6] programming is supported. HPROT[6] HIGH denotes a nonsecure transfer. HPROT[6] LOW denotes a secure transfer. HPROT[6] can be asserted LOW by writing to the SProt field in the CSW Register. A secure transfer can only be initiated if SPIDEN is HIGH. If SProt is set LOW in the CSW Register to perform a secure transfer, but SPIDEN is LOW, then no AHB transfer takes place.

See AHB-AP Control/Status Word Register, CSW, 0x00 for values of the Prot field.


HRESP[0] is the only RESPONSE signal required by the AHB-AP:

  • AHB-Lite devices do not support SPLIT and RETRY and so HRESP[1] is not required. It is still provided as an input, and if not present on any slave it must be tied LOW. Any response that is not OKAY, that is, not 2'b00, is treated as an ERROR response.

  • HRESP[2] is not required because exclusive accesses are unsupported in the AHB-AP.

HBSTRB support

HBSTRB[3:0] signals are automatically generated based on the transfer size HSIZE[2:0] and HADDR[1:0]. Byte, halfword and word transfers are supported. It is not possible for the user to directly control HBSTRB[3:0].

Unaligned transfers are not supported. Table 2.18 shows an example of the generated HBSTRB[3:0] signals for different-sized transfers.

Table 2.18. Example generation of byte lane strobes

Transfer descriptionHADDR[1:0]HSIZE[2:0]HBSTRB[3:0]
8-bit access to 0x1000b00b000b0001
8-bit access to 0x1003b11b000b1000
16-bit access to 0x1002b10b001b1100
32-bit access to 0x1004b00b010b1111

AHB-AP transfer types and bursts

The AHB-AP cannot initiate a new AHB transfer every clock cycle (unpacked) because of the additional cycles required to serial scan in the new address or data value through a debug port. The AHB-AP supports two HTRANS transfer types, IDLE and NONSEQ:

  • When a transfer is in progress, it is of type NONSEQ

  • When no transfer is in progress and the AHB-AP is still granted the bus then the transfer is of type IDLE.

The only unpacked HBURST encoding supported is SINGLE. Packed 8-bit transfers or 16-bit transfers are treated as individual NONSEQ, SINGLE transfers at the AHB-Lite interface. This ensures that there are no issues with boundary wrapping, to avoid additional AHB-AP complexity.

A full AHB master interface can be created by adding an AHB-Lite to AHB wrapper to the output of the AHB-AP, as provided in the AMBA Design Kit.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H