2.7.3. Programmers model overview

This section describes the registers used to program the AHB-AP. It contains the following subsections:

AHB-AP register summary

Table 2.19 shows the AHB access port registers.

Table 2.19. AHB access port registers

Offset TypeWidth Reset valueName
0x00R/W320x40000002Control/Status Word, CSW
0x04R/W320x00000000Transfer Address, TAR
0x08---Reserved SBZ
0x0CR/W32-Data Read/Write, DRW
0x10R/W32-Banked Data 0, BD0
0x14R/W32-Banked Data 1, BD1
0x18R/W32-Banked Data 2, BD2
0x1CR/W32-Banked Data 3, BD3
0x20-0xF7---Reserved SBZ

Implementation defined

Debug ROM table
0xFCRO320x34770001Identification Register, IDR.

AHB access port register descriptions

The section describes the AHB access port registers:

AHB-AP Control/Status Word Register, CSW, 0x00

This is the control word used to configure and control transfers through the AHB interface.

Figure 2.19 shows the Control/Status Word Register bit assignments.

Figure 2.19. AHB-AP Control/Status Word Register bit assignments

Table 2.20 shows the bit assignments.

Table 2.20. AHB-AP Control/Status Word Register bit assignments

[31]--Reserved SBZ.

Specifies that a secure transfer is requested.

SProt HIGH indicates a non-secure transfer. SProt LOW indicates a secure transfer.

  • If this bit is LOW, and SPIDEN is HIGH, HPROT[6] is asserted LOW on an AHB transfer.

  • If this bit is LOW, and SPIDEN is LOW, HPROT[6] is asserted HIGH and the AHB transfer is not initiated.

  • If this bit is HIGH, the state of SPIDEN is ignored. HPROT[6] is HIGH.

Reset value = b1. Non-secure.

[29]--Reserved SBZ.

Specifies the protection signal encoding to be output on HPROT[4:0].

Reset value: non-secure, non-exclusive, noncacheable, non-bufferable, data access, privileged = b00011.

[23]ROSPIStatusIndicates the status of the SPIDEN port. If SPIStatus is LOW, no secure AHB transfers are carried out.
[22:12]--Reserved SBZ.

Specifies the mode of operation.

b0000 = Normal download/upload model

b0001-b1111 = Reserved SBZ.

Reset value = b0000.

[7]ROTrInProgTransfer in progress. This field indicates if a transfer is currently in progress on the AHB master port

Indicates the status of the DBGEN port. If DbgStatus is LOW, no AHB transfers are carried out.

1 = AHB transfers permitted.

0 = AHB transfers not permitted.


Auto address increment and packing mode on Read or Write data access. Only increments if the current transaction completes without an Error response and the transaction is not aborted.

Auto address incrementing and packed transfers are not performed on access to Banked Data registers 0x10-0x1C. The status of these bits is ignored in these cases.

Increments and wraps within a 1KB address boundary, for example, for word incrementing from 0x1400-0x17FC. If the start is at 0x14A0, then the counter increments to 0x17FC, wraps to 0x1400, then continues incrementing to 0x149C.

b00 = Auto increment OFF.

b01 = Increment, single.

Single transfer from corresponding byte lane.

b10 = Increment, packed

Word = Same effect as single increment.

Byte/Halfword: Packs four 8-bit transfers or two 16-bit transfers into a 32-bit DAP transfer. Multiple transactions are carried out on the AHB interface.

b11 = Reserved SBZ, no transfer.

Size of address increment is defined by the Size field, bits [2:0].

Reset value = b00.

[3]--Reserved SBZ, R/W = b0

Size of the data access to perform:

b000 = 8 bits

b001 = 16 bits

b010 = 32 bits

b011-b111 = Reserved SBZ.

Reset value = b010.

AHB-AP Transfer Address Register, TAR, 0x04

Table 2.21 shows the AHB-AP Transfer Address Register bit assignments.

Table 2.21. AHB-AP Transfer Address Register bit assignments


Address of the current transfer.

Reset value is 0x00000000.

AHB-AP Data Read/Write Register, DRW, 0x0C

Table 2.22 shows the AHB-AP Data Read/Write Register bit assignments.

Table 2.22. AHB-AP Data Read/Write Register bit assignments


Write mode: Data value to write for the current transfer.

Read mode: Data value read from the current transfer.

AHB-AP Banked Data Registers, BD0-BD03, 0x10-Ox1C

BD0-BD3 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the Transfer Address Register (TAR) within a four-location boundary. BD0 reads/writes from TA. BD1 reads/writes from TA+4. Table 2.23 shows the AHB-AP Banked Data Register bit assignments.

Table 2.23. Banked Data Register bit assignments


If DAPADDR[7:4] = 0x0001, so accessing AHB-AP registers in the range 0x10-0x1C, the derived HADDR[31:0] is:

  • Write mode: Data value to write for the current transfer to external address TAR[31:4] + DAPADDR[3:2] + 2'b00.

  • Read mode: Data value read from the current transfer from external address TAR[31:4] + DAPADDR[3:2] + 2'b00.

Auto address incrementing is not performed on DAP accesses to BD0-BD3.

Banked transfers are only supported for word transfers. Non-word banked transfers are reserved and unpredictable. Transfer size is currently ignored for banked transfers.

ROM Address Register, ROM, 0xF8

Table 2.24 shows the ROM Address Register bit assignments.

Table 2.24. ROM Address Register bit assignments

[31:0]RODebug AHB ROM AddressBase address of a ROM table. The ROM provides a look-up table for system components. Set to 0xFFFFFFFF in the AHB-AP in the initial release.

AHB-AP Identification Register, IDR, 0xFC

Figure 2.20 shows the AHB-AP Identification Register bit assignments.

Figure 2.20. AHB-AP Identification Register bit assignments

Table 2.25 shows the AHB-AP Identification Register bit assignments.

Table 2.25. AHB-AP Identification Register bit assignments

[31:28]RORevision0x4Revision 4
[27:24]ROJEDEC bank0x4Designed by ARM
[23:17]ROJEDEC code0x3BDesigned by ARM
[16]ROMem AP0x1Is a Mem AP
[7:0]ROIdentity value0x01AHB-AP

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