2.12.1. ROM table registers

Table 2.42 shows the ROM table registers. The values of the table entries depend on the CoreSight subsystem that is implemented.

Table 2.42. ROM table registers

OffsetTypeBitsNameFunction
0xFDC-[7:0]Peripheral ID7Reserved SBZ. Read as 0x00.
0xFD8-[7:0]Peripheral ID6Reserved SBZ. Read as 0x00.
0xFD4-[7:0]Peripheral ID5Reserved SBZ. Read as 0x00.
0xFD0RO[7:4]Peripheral ID44KB count, set to 0x0.
[3:0]JEP106 continuation code, implementation defined.
0xFECRO[7:4]Peripheral ID3RevAnd, at top level, implementation defined.
[3:0]Customer Modified, implementation defined.
0xFE8RO[7:4]Peripheral ID2Revision number of Peripheral, implementation defined.
[3]

1 = indicates that a JEDEC assigned value is used.

0 = indicates that a JEDEC assigned value is not used.

[2:0] JEP106 Identity Code [6:4], implementation defined.
0xFE4RO[7:4]Peripheral ID1JEP106 Identity Code [3:0], implementation defined.
[3:0]PartNumber1, implementation defined.
0xFE0RO[7:0]Peripheral ID0PartNumber0, implementation defined.
0xFF0RO[7:0]Component ID0Preamble. Set to 0x0D.
0xFF4RO[7:0]Component ID1Preamble. Set to 0x10.
0xFF8RO[7:0]Component ID2Preamble. Set to 0x05.
0xFFCRO[7:0]Component ID3Preamble. Set to 0xB1.

The ROM table has a specific PrimeCell class. In all registers 0xFD0-0xFFC, bits [31:8] are reserved and should be read as zero. Locations 0xF00-0xFCC are reserved and should be read as zero.

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