8.6.8. TPIU Test Pattern Repeat Counter Register, 0x208

This is an eight-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. On reset this value is set to 0.

Figure 8.7 shows the TPIU Test Pattern Repeat Counter Register bit assignments.

Figure 8.7. Test Pattern Repeat Counter Register bit assignments


Table 8.9 shows the TPIU Test Pattern Repeat Counter Register bit assignments.

Table 8.9. Test Pattern Repeat Counter Register bit assignments

BitsTypeNameDescription
[31:8]--Reserved RAZ/SBZP
[7:0]R/WPattCount8-bit counter value to indicate the number of TRACECLKIN cycles that a pattern runs for before switching to the next pattern. Default value is 0.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential