8.9.4. Off-chip based TRACECLKIN

Future CoreSight-aware TPAs might directly control a clock source for the Trace Out port. By running through a known sequence of patterns, from the pattern generator within the TPIU, a TPA could automatically establish the port width and ramp up the clock speed until the patterns degrade, thereby establishing a maximum data rate. Figure 8.19 shows how an off-chip TRACECLKIN could be generated.

Figure 8.19. Externally derived TRACECLK

The off-chip clock would operate in a similar way to the currently exported TRACECLK, that is, an externally derived clock source would be clock-doubled to enable the exported data to change at both edges of the clock.

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