8.6.1. Supported Port Size Register, 0x000

This register is read/write. Each bit location represents a single port size that is supported on the device, that is, 32-1 in bit locations [31:0]. If the bit is set then that port size is allowed. By default the RTL is designed to support all port sizes, set to 0xFFFFFFFF. This register reflects the value of the CSTPIU_SUPPORTSIZE_VAL Verilog `define value, currently not user modifiable, and is further constrained by the input tie-off TPMAXDATASIZE.

The external tie-off, TPMAXDATASIZE, must be set during finalization of the ASIC to reflect the actual number of TRACEDATA signals being wired to physical pins. This is to ensure that tools do not attempt to select a port width that cannot be captured by an attached TPA. The value on TPMAXDATASIZE causes bits within the Supported Port Size register that represent wider widths to be clear, that is, unsupported.

Figure 8.2 shows the Supported Port Size Register bit assignments.

Figure 8.2. Supported Port Size Register bit assignments


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