8.6.3. Supported Trigger Modes Register, 0x100

The Supported Trigger Modes Register is read only. This register indicates the implemented Trigger Counter multipliers and other supported features of the trigger system. Figure 8.3 shows the Supported Trigger Modes Register bit assignments.

Figure 8.3. Supported Trigger Modes Register bit assignments


Table 8.5 shows the Supported Trigger Modes Register bit assignments.

Table 8.5. Supported Trigger Modes Register bit assignments

BitsTypeNameDescription
[31:18]--Reserved RAZ/SBZP
[17]ROTrgRunTrigger Counter running. A trigger has occurred but the counter is not at zero.
[16]ROTriggeredTriggered. A trigger has occurred and the counter has reached zero.
[15:9]--Reserved RAZ/SBZP
[8]ROTCount88-bit wide counter register implemented.
[7:5]--Reserved RAZ/SBZP
[4]ROMult64kMultiply the Trigger Counter by 65536 supported.
[3]ROMult256Multiply the Trigger Counter by 256 supported.
[2]ROMult16Multiply the Trigger Counter by 16 supported.
[1]ROMult4Multiply the Trigger Counter by 4 supported.
[0]ROMult2Multiply the Trigger Counter by 2 supported.

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