8.6.10. Formatter and Flush Control Register, 0x304

This register controls the generation of stop, trigger, and flush events. Figure 8.9 shows the Formatter and Flush Control Register bit assignments.

Figure 8.9. Formatter and Flush Control Register bit assignments

Table 8.11 shows the Formatter and Flush Control Register bit assignments.

Table 8.11. Formatter and Flush Control Register bit assignments

[31:14]--Reserved RAZ/SBZP.
[13]R/WStopTrigStop the formatter after a Trigger Event[a] is observed. Reset to disabled, or zero.
[12]R/WStopFlStop the formatter after a flush completes (return of AFREADYS). This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset, or disabled.
[11]--Reserved RAZ/SBZP.
[10]R/WTrigFlIndicates a trigger on Flush completion on AFREADYS being returned.
[9]R/WTrigEvtIndicate a trigger on a Trigger Eventa.
[8]R/WTrigInIndicate a trigger on TRIGIN being asserted.
[7]--Reserved RAZ/SBZP.
[6]R/WFOnManManually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit is clear on reset.
[5]R/WFOnTrigGenerate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Eventa occurs. Reset value is this bit clear.
[4]R/WFOnFlInGenerate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection. This is clear on reset.
[3:2]--Reserved RAZ/SBZP.
[1]R/WEnFContContinuous Formatting, no TRACECTL. Embed in trigger packets and indicate null cycles using Sync packets. Reset value is this bit clear. Can only be changed when FtStopped is HIGH.
[0]R/WEnFTCEnable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Reset value is this bit clear. Can only be changed when FtStopped is HIGH.

[a] A Trigger Event is defined as when the Trigger counter reaches zero or, in the case of the Trigger counter being zero, when TRIGIN is HIGH.

To disable formatting and put the formatter into bypass mode, bits 1 and 0 must be clear. Setting both bits is the same as setting bit 1.

All three flush generating conditions can be enabled together. However, if a second or third flush event is generated from another condition then the current flush completes before the next flush is serviced. Flush from FLUSHIN takes priority over flush from Trigger, which in turn completes before a manually activated flush. All Trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled.

Both 'Stop On' settings can be enabled, although if flush on trigger is set up then none of the flushed data is stored. When the system stops, it returns ATREADYS and does not store the accepted data packets. This is to avoid stalling of any other devices that are connected to a Trace Replicator.

If an event in the Formatter and Flush Control Register is required, it must be enabled before the originating event starts. Because requests from flushes and triggers can originate in an asynchronous clock domain, the exact time the component acts on the request cannot be determined with respect to configuring the control.


  • It is recommended that the Trace Port width is changed without enabling continuous mode. Enabling continuous mode causes data to be output from the Trace Port and modifying the port size can result in data not being aligned for power2 port widths.

  • To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required:

    • one to enable the stop event, if it is not already enabled

    • one to generate the manual flush.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H