8.6.11. Formatter Synchronization Counter Register, 0x308

The Formatter Synchronization Counter Register enables effective use on different sized Trace Port Analyzers (TPAs) without wasting large amounts of the storage capacity of the capture device.

This counter is the number of formatter frames since the last synchronization packet of 128 bits, and is a 12-bit counter with a maximum count value of 4096. This equates to synchronization every 65536 bytes, that is, 4096 packets x 16 bytes per packet. The default is set up for a synchronization packet every 1024 bytes, that is, every 64 formatter frames.

Figure 8.10 shows the Formatter Synchronization Counter Register bit assignments.

Figure 8.10. Formatter Synchronization Counter Register bit assignments


Table 8.12 shows the Formatter Synchronization Counter Register bit assignments.

Table 8.12. Formatter Synchronization Counter Register bit assignments

BitsTypeNameDescription
[31:12]--Reserved RAZ/SBZP.
[11:0]R/WCycCount12-bit counter value to indicate the number of complete frames between full synchronization packets. Default value is 64 (0x40).

If the formatter has been configured for continuous mode, full and half-word sync frames are inserted during normal operation. Under these circumstances the count value represents the maximum number of complete frames between full synchronization packets.

See Supported Trigger Modes Register, 0x100 for more on different modes.

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