8.6.4. Trigger Counter Register, 0x104

The Trigger Counter Register enables delaying the indication of triggers to any external connected trace capture or storage devices. This counter is only eight bits wide and is intended to only be used with the counter multipliers in the Trigger Multiplier Register, 0x108. When a trigger is started, this value, in combination with the multiplier, is the number of words before the trigger is indicated. When the trigger counter reaches zero, the value written here is reloaded. Writing to this register causes the trigger counter value to reset but not reset any values on the multiplier. Reading this register returns the preset value not the current count.

Figure 8.4 shows the Trigger Counter Register bit assignments.

Figure 8.4. Trigger Counter Register bit assignments


Table 8.6 shows the Trigger Counter Register bit assignments.

Table 8.6. Trigger Counter Register bit assignments

BitsTypeNameDescription
[31:8]--Reserved RAZ/SBZP
[7:0]R/WTrigCount8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. Reset value is 0x00.

At reset the value is zero and this value has the effect of disabling the register, that is, there is no delay.

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