8.9.1. TRACECLK generation

In an ideal environment TRACECLK is derived from the negative edge of TRACECLKIN to create a sample point within the centre of the stable data, TRACEDATA, TRACECTL, on each changing edge of TRACECLK irrespective of the operating frequency. This method does create a large number of issues during clock-tree synthesis, layout and static timing analysis.

TRACECLK is a divided by two, exported version of TRACECLKIN. The reason for creating a half clock is that the limiting factor for both the Trace Out Port is the slew rate from a zero-to-one and one-to-zero. If it is possible to detect logic 1 and logic 0 on the exported clock within one cycle then it is also possible to detect two different values on the exported data pins.

There is no requirement to either invert the clock or use negative-edge registers in the generation of TRACECLK. The register that creates the divided by two clock is a standard positive-edge register that operates synchronously to the TRACEDATA and TRACECTL registers. This method simplifies synthesis in the early stages and ensures when clock tree synthesis is performed, all the registers are operating at the same time. To create the sample point at a stable point in the exported data, a delay must be added to the path of TRACECLK between the register and the pad.

Figure 8.17 shows TRACECLK at different points within the design and its relationship to the data and control signals, TRACEDATA and TRACECTL. At the moment of creation from the final registers of the Trace Out Port signals, all data edges are aligned as shown at point A in Figure 8.17.

All the signal paths to the pads are subject to delays as a result of the differing path lengths at point B from wire delay. These delays must be minimized where possible by placing the registers as close to the pads as possible. Each path must be re-balanced to remove the relative skew between signals by adding in equivalent delays. An extra delay must be incorporated on the TRACECLK path to ensure the waveform at point C is achieved and that the rising and falling edges of TRACECLK correspond to the center of stable data on TRACECTL and TRACEDATA as shown in Figure 8.18.

Figure 8.17. Paths of TRACECLK, TRACEDATA, and TRACECTL to pads

Figure 8.18 shows how the rising and falling edges of TRACECLK correspond to the center of stable data on TRACECTL and TRACEDATA at point C.

Figure 8.18. TRACECLK timing in relation to TRACEDATA and TRACECTL

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