12.6.1. Trace Enable Register, TER, 0xE00

Each bit location corresponds to a virtual stimulus register; when a bit is set, a write to the appropriate stimulus location results in a packet being generated, except when the FIFO is full. Reset to disable all locations is 0x00000000.

The setting of the bits [31:16] is ignored if secure trace is disabled. Stimulus ports 16-31 are disabled when the ability to perform secure non-invasive debug is removed.

The setting of the bits [31:0] is ignored if non-secure trace is disabled. Stimulus ports 0-31 are disabled when the ability to perform non-secure non-invasive debug is removed.

Table 12.6 shows the Trace Enable Register bit assignments.

Table 12.6. Trace Enable Register bit assignments

BitsNameDescription
[31:0]Trace Enable RegisterBit mask to enable tracing on ITM stimulus ports.

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