2.9.1. External interfaces

Table 2.35 shows the JTAG to slave device signals.

Each o f the eight JTAG scan chains are on the same bit positions for each JTAG signal. For example, connections for scan chain 0 can be located on bit [0] of each bus connection of CSTCK, CSTMS, CSTDI, PORTCONNECTED.

Table 2.35. JTAG to slave device signals

nSRSTOUT[7:0]OutputSubsystem Reset Out
SRSTCONNECTED[7:0]InputSubsystem Reset is present/wired
nCSTRST[7:0]OutputJTAG Test Reset
CSTCK[7:0]OutputJTAG Test Clock
CSTMS[7:0]OutputJTAG Test Mode Select
CSTDI[7:0]OutputJTAG Test Data In, to external TAP
CSTDO[7:0]InputJTAG Test Data Out, from external TAP
CSRTCK[7:0]InputReturn Test Clock, target pacing signal
PORTCONNECTED[7:0]InputJTAG Port is connected, status signal
PORTENABLED[7:0]InputJTAG Port is enabled, for example, it might be deasserted by a processor powering down

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