11.3. SWO programmers model

This section describes all the visible registers that can be accessed from the APB interface. Table 11.2 shows the SWO programmable registers.

Table 11.2. SWO programmable registers

OffsetTypeWidthReset valueNameDescription
0x000RO320x00000000Supported Synchronous Port SizesSee Trace port control registers
0x004RO320x00000000Current Synchronous Port Size
0x010R/W130x0000Current Asynchronous Output Speed Divisors
0x0F0R/W20x1Selected Pin Protocol
0x100RO90x000Supported Trigger ModesSee Trigger registers
0x200RO180x00000Supported Test Pattern/ModesSee Test pattern registers
0x300RO40x8Formatter and Flush StatusSee Formatter and flush registers
0x304RO140x0000Formatter and Flush Control
0xEECRO20x0

Integration Test ATB Data Register 0

See Integration test registers
0xEF0WO1-

Integration Test ATB Control Register 2

0xEF8RO1-

Integration Test ATB Control Register 0

0xF00R/W10x0Integration Mode Control RegisterSee CoreSight defined registers
0xFA0R/W40xFClaim Tag Set
0xFA4R/W40x0Claim Tag Clear
0xFB0WO32-Lock Access
0xFB4RO30x0/0x3Lock Status
0xFB8RO80x00Authentication status
0xFC8RO130x0EA0Device ID
0xFCCRO80x11Device Type Identifier
0xFD0RO80x04Peripheral ID4See CoreSight defined registers
0xFD4RO80x00Peripheral ID5, reserved for future use
0xFD8RO80x00Peripheral ID6, reserved for future use
0xFDCRO80x00Peripheral ID7, reserved for future use
0xFE0RO80x14Peripheral ID0, contains Part Number[7:0]See CoreSight defined registers
0xFE4RO80xB9Peripheral ID1, contains Part Number[12:8]
0xFE8RO80x1BPeripheral ID2
0xFECRO80x00Peripheral ID3
0xFF0RO80x0DComponent ID0See CoreSight defined registers
0xFF4RO80x90Component ID1
0xFF8RO80x05Component ID2
0xFFCRO80xB1Component ID3

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