12.1.1. Trace packet format

Trace data from ITM is output in packets with a byte protocol. These packets are 1-5 bytes in size, comprising:

Note

Synchronization packets differ slightly, and comprise a unique 6-byte sequence for bit and byte synchronization.

Table 12.1 and Table 12.2 show the trace packet encodings.

Table 12.1. Sync packet encoding

DescriptionPacket valuePayloadCategoryNotes
Synchronization0x800000000000NoneSynchronization{47{1'b0}} followed by 1'b1. Matches ETM protocol.

Table 12.2. Trace packet encoding

DescriptionHeader valuePayloadCategoryNotes
Overflow0b01110000NoneProtocolOverflow
Timestamp0bCDDD00000-4 bytesProtocol

D = data (!=000) - time

C = continuation

Reserved0bCxxx01000-4 bytesReservedC = continuation
SWIT0bBBBBB0SS1, 2, or 4 bytesSoftware source (application)

SS = size (!=00) of payload B = SW Source Address


The ITM trace packets are described in:

Synchronization packet

Synchronization packets are unique patterns in the bit-stream that enable capture hardware to identify bit-to-byte alignment. A synchronization packet is only emitted if the APB interface has been used since the last synchronization packet. Synchronization packets are output by the timestamp packet when the synchronization counter reaches zero. A synchronization packet is forty-seven 1'b0 followed by one 1'b1. Figure 12.2 shows the layout of a synchronization packet.

Figure 12.2. Synchronization packet layout


Overflow packet

Overflow packets can precede all packets except synchronization packets. Overflow is tracked by each source, either SWIT or timestamp.

SWIT overflow is against all stimulus ports. This happens when data is written to the Stimulus Registers but the FIFO is full. Timestamp overflows on reaching the value 2097151.

Figure 12.3 shows the layout of an overflow packet.

Figure 12.3. Overflow packet layout


Note

Before disabling the ITM, tools must ensure the FIFO is not full before writing a dummy packet to a Stimulus Register to flush out any overflow information. They must then wait for the ITMBUSY bit to go LOW again, before finally clearing the ITMEn bit.

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