2.14. Clocks, power, and resets

The DAP implements 4 clock and power domains they are:

For more information on the partitioning and controlling signals for the separate clock domains, refer to the appropriate sections.

PCLKDBG must be driven by a constant clock. It must not be stopped or altered while the DAP is in use (determined by the debug power request from the Debug Port). PCLKENDBG can be used as a clock gating term to reduce the effective clock speed from PCLKDBG. PRESETDBGn initializes the state of all registers in the PCLKDBG domain. PRESETDBGn enables initialization of the DAP without affecting the normal operation of the SoC in which the DAP is integrated, and should be driven by the tools on external connection to the debug port. The reset can be initiated by writing to the control register of the Debug Port (the debug reset request register). This resets all the registers in the Debug clock domain, that is, Debug APB and DAP domains.


Internally to the DAP there is a clock signal which is not presented at the top level but is internally connected to PCLKDBG. Correspondingly the internal reset and clock enable terms are also connected to PRESETDBGn and PCLKENDBG respectively.

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