2.9.3. Programmers model overview

Table 2.36 shows the JTAG-AP registers.

Table 2.36. JTAG-AP register summary

Offset Type WidthReset valueName
0x00R/W320x00000000Control/Status Word, CSW
0x04R/W80x00Port Select, PORTSEL
0x08R/W80x00Port Status, PSTA
0x0C---Reserved
0x10R/W8UndefinedByte FIFO 1 Entry, BFIFO1
0x14R/W16UndefinedByte FIFO 2 Entry, BFIFO2
0x18R/W24UndefinedByte FIFO 3 Entry, BFIFO3
0x1CR/W32UndefinedByte FIFO 4 Entry, BFIFO4
0x20-0xF8---Reserved SBZ
0xFCRO320x14760010

Identification Register, IDR. Required by all access ports


All the registers are described fully in the ARM Debug Interface v5 Architecture Specification and the ARM Debug Interface v5.1 Architecture Supplement.

JTAG-AP Control/Status Word Register, CSW, 0x00

The JTAG-AP control word is used to configure and control transfers through the JTAG interface. Figure 2.26 shows the JTAG-AP Control/Status Word Register bit assignments.

Figure 2.26. JTAG-AP Control/Status Word Register bit assignments


Table 2.37 shows the JTAG-AP Control/Status Word Register bit assignments. The register must not be modified while there are outstanding commands in the Write FIFO.

Table 2.37. JTAG-AP Control/Status Word Register bit assignments

BitsTypeNameFunction
[31]ROSERACTV

JTAG Serializer active.

Reset value = b0.

[30:28]ROWFIFOCNT

Outstanding Write FIFO Byte Count.

Reset value = b000.

[27]--Reserved SBZ
[26:24]RORFIFOCNT

Outstanding Read FIFO Byte Count.

Reset value = b000

[23:4]--Reserved SBZ 0x00000
[3]ROPORTCONNECTEDPORT Connected. AND of PORTCONNECTED inputs of currently selected ports.Reset value = b0.
[2]ROSRSTCONNECTED[a]

SRST Connected.

AND of SRSTCONNECTED inputs of currently selected ports. If multiple ports are selected, it is the AND of all the SRSTCONNECTED inputs from the selected ports.

Reset value = b0.

[1]R/WTRST_OUT

TRST Assert, not self clearing.

JTAG TAP controller reset.

Reset value = b0.

[0]R/WSRST_OUT

SRST Assert, not self clearing.

Core Reset.

Reset value = b0.

[a] SRSTCONNECTED is a strap pin on the multiplexor inputs. It is set to 1 to indicate that the target JTAG device supports individual SRST controls.


JTAG-AP Port Select Register, PORTSEL, 0x04

The Port Select Register enables ports if connected and the slave port is currently enabled. The Port Select Register must be written when the TCK engine is idle, SERACTV=0, and WFIFO, WFIFOCNT=0, is empty. Writing at other times can generate unpredictable results.

Figure 2.27 shows the shows the JTAG-AP Port Select Register bit assignments.

Figure 2.27. JTAG-AP Port Select Register bit assignments


Table 2.38 shows the JTAG-AP Port Select Register bit assignments.

Table 2.38. JTAG-AP Port Select Register bit assignments

BitsTypeNameFunction
[31:8]--Reserved SBZ.
[7:0]R/WPORTSEL

Port Select.

Reset value = b00000000.


JTAG-AP Port Status Register, PSTA, 0x08

The Port Status Register is a sticky register that captures the state of a connected and selected port on every clock cycle. If a connected and selected port is disabled or powered down, even transiently, the corresponding bit in the Port Status Register is set. It remains set until cleared by writing a one to the corresponding bit.

Figure 2.28 shows the JTAG-AP Port Status Register bit assignments.

Figure 2.28. JTAG-AP Port Status Register bit assignments


Table 2.39 shows the JTAG-AP Port Status Register bit assignments.

Table 2.39. JTAG-AP Port Status Register bit assignments

BitsTypeNameFunction
[31:8]--Reserved SBZ.
[7:0]R/WPSTA

Port Status.

Reset value = b00000000.


JTAG-AP Byte FIFO registers, BFIFOn, 0x10-0x1C

The Byte FIFO registers are a word interface to one, two, three, or four parallel byte entries in the Byte Command FIFO, LSB first. The DAP Internal Bus is a 32-bit interface with no SIZE field. So, an address decoding is used to designate size, because the JTAG-AP Engine JTAG protocol is byte encoded. Writes to the BFIFOx larger than the current write FIFO depth stall on DAPREADY in Normal mode. Reads to the BFIFOx larger than the current read FIFO depth stall on DAPREADY in Normal mode. For reads less than the full 32-bits, the upper bits are zero. For example, for a 24-bit read, DAPRDATA[31:24] is 0x00.

JTAG-AP Identification Register

Figure 2.29 shows the JTAG-AP Identification Register bit assignments.

Figure 2.29. JTAG-AP Identification Register bit assignments


Table 2.40 shows the JTAG-AP Identification Register bit assignments.

Table 2.40. JTAG-AP Identification Register bit assignments

BitsTypeNameValueMeaning
[31:28]RORevision0x3Revision 3
[27:24]ROJEDEC bank0x4Designed by ARM
[23:17]ROJEDEC code0x3BDesigned by ARM
[16]ROMem AP0x0Is a Mem AP
[15:8]-Reserved0x00-
[7:0]ROIdentity value0x10JTAG-AP

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