12.7.2. Synchronization Control Register, SCR, 0xE90

Synchronization packets must be output on a regular basis to provide decompression tools markers in the trace stream. The first synchronization packet is output when the ITM is enabled by setting bit [0] in the Control Register. Subsequent packets are output when the counter reaches zero, that is, decrement on data entered into the FIFO. The Synchronization Control Register represents the reloaded count value when the counter reaches zero, not the current count. This register must only be changed when the ITM is disabled.

Note

A value of 0x000 written to the Synchronization Control Register causes unpredictable results. This value must only be used when a synchronization counter is not implemented. This register always reads as zero if no synchronization counter is implemented. A counter can be detected by attempting to write a non-zero value to the register and reading it back. The default value is 0x400.

Figure 12.8 shows the Synchronization Control Register bit assignments.

Figure 12.8. Synchronization Control Register bit assignments


Table 12.9 shows the Synchronization Control Register bit assignments.

Table 12.9. Synchronization Control Register bit assignments

BitsNameDescription
[31:12]-Reserved RAZ/SBZP
[11:0]Sync CountCounter value for time between synchronization markers

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