4.4.1. CTI Control Register, CTICONTROL, 0x000

The CTI Control Register enables the CTI.

Figure 4.3 shows the bit assignments.

Figure 4.3. CTI Control Register bit assignments


Table 4.2 shows the bit assignments.

Table 4.2. CTI Control Register bit assignments

BitsNameDescription
[31:1]-Reserved RAZ DNM.
[0]GLBEN

Enables or disables the ECT:

0 = disabled (reset)

1 = enabled.

When disabled, all cross triggering mapping logic functionality is disabled for this processor.


Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential