2.2.4. Clock, reset and power domain support

In the SWCLKTCK clock domain, there are registers to enable power control for the on-chip debug infrastructure. This enables the majority of the debug logic, such as ETM and ETB, to be powered down by default, and only the serial engine has to be clocked. A debug session then starts by powering up the remainder of the debug components. In SWJ-DP, either JTAG-DP or SW-DP can make power-up or reset requests but only if they are the selected device. Even in a system which does not provide a clock and reset control interface to the DAP, it is necessary to connect these signals so it appears that a clock and reset controller is present. This permits correct handshaking of the request and acknowledge signals.

To help provide separate power domains, it is possible to partition the RTL of SWJ-DP to enable an always on domain and debug domain as defined in ADIv5.1. Figure 2.7 shows the RTL structure to support power domain structure.

Figure 2.7. SWJ-DP signal clamping


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