9.3.10. ETB Formatter and Flush Control Register, FFCR, 0x304

This register indicates the stop, trigger, and flush events. Figure 9.5 shows the ETB Formatter and Flush Control Register bit assignments.

Figure 9.5. ETB Formatter and Flush Control Register bit assignments


Table 9.14 shows the ETB Formatter and Flush Control Register bit assignments.

Table 9.14. ETB Formatter and Flush Control Register bit assignments

BitsTypeNameDescription
[31:14]--Reserved RAZ/SBZP.
[13]R/WStopTrigStop the formatter when a Trigger Event[a] has been observed. Reset to disabled (zero).
[12]R/WStopFlStop the formatter when a flush has completed (return of AFREADYS). This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset (disabled).
[11]--Reserved RAZ/SBZP.
[10]R/WTrigFlIndicate a trigger on Flush completion (AFREADYS being returned).
[9]R/WTrigEvtIndicate a trigger on a Trigger Eventa.
[8]R/WTrigInIndicate a trigger on TRIGIN being asserted
[7]--Reserved RAZ/SBZP.
[6]R/WFOnManManually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit is clear on reset.
[5]R/WFOnTrigGenerate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Eventa occurs. This bit is clear on reset.
[4]R/WFOnFlInGenerate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection. This bit is clear on reset.
[3:2]--Reserved RAZ/SBZP.
[1]R/WEnFContContinuous Formatting. Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed when FtStopped is HIGH. This bit is clear on reset.
[0]R/WEnFTCEnable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset.

[a] A Trigger Event is defined as when the Trigger counter reaches zero (where fitted) or, in the case of the trigger counter being zero (or not fitted), when TRIGIN is HIGH.


To disable formatting and put the formatter into bypass mode, bits 1 and 0 must be clear. If both bits are set, then the formatter inserts triggers into the formatted stream.All three flush generating conditions can be enabled together. However, if a second or third flush event is generated then the current flush completes before the next flush is serviced. Flush from FLUSHIN takes priority over flush from Trigger, which in turn completes before a manually activated flush.All trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled.

Both 'Stop On' settings can be enabled although if flush on trigger, FOnTrig, is set then none of the flushed data is stored. When the system stops, it returns ATREADY and does not store the accepted data packets. This is to stop stalling of any other connected devices using a Trace Replicator.

If an event in the Formatter and Flush Control Register is required, it must be enabled before the originating event starts. Because requests from flushes and triggers can originate in an asynchronous clock domain, the exact time the component acts on the request cannot be determined with respect to configuring the control.

Note

To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required:

  • one to enable the stop event, if it is not already enabled

  • one to generate the manual flush.

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