2.5. Common debug port features and registers

This section describes specific details of features and registers that are present within this implementation of SW-DP and JTAG-DP as part of the SWJ-DP. For all the features and registers present within SW-DP and JTAG-DP, see the ARM Debug Interface v5 Architecture Specification and the ARM Debug Interface v5.1 Architecture Supplement. This section contains the following implementation specific details:

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