11.5.3. Current Output Divisor Register, CODR, 0x010

With this register is possible to scale the baud rate of the SWO output. It divides TRACECLKIN, enabling it when the counter reaches the programmed value, and reducing the baud rate of the TRACESWO pin. Its reset value is 0x0000 and the counter is always running. The actual division value for the TRACECLKIN frequency is the value of this register plus one.

Whenever this register is reprogrammed, the internal counter is automatically reset, making the baud-rate change instantaneously.

Note

  • The SWO does not support stopping. Changing the prescaler while trace is being processed is permitted. However, the moment of change in relation to the trace port is unpredictable. It is recommended that the trace source is disabled, and the trace port idle, before changing this register.

  • When the Divisor field has been altered, the capture device must also be adjusted where appropriate to ensure the correct data is captured.

Figure 11.2 shows the Current Output Divisor Register bit assignments.

Figure 11.2. Current Output Divisor Register bit assignments


Table 11.5 shows the Current Output Divisor Register bit assignments.

Table 11.5. Current Output Divisor Register bit assignments

BitsNameDescription
[31:13]-Reserved RAZ/SBZP.
[12:0]Prescaler13 bit counter. Reset value is 0x0000.

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