4.5. ECT Integration Test Registers

Integration Test Registers are provided to simplify the process of verifying the integration of the ECT with other devices in a CoreSight system. These registers enable direct control of outputs and the ability to read the value of inputs. You must only use these registers when the Integration Mode Control Register (0xF00) bit [0] is set to 1.

For details of how to use these signals, see the CoreSight Components Implementation Guide and the applicable Integration Manual.

This section describes the following registers:

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H