2.3.2. Implementation specific details

The implementation specific details are described in:

Physical interface

Table 2.1 shows the physical interface for JTAG-DP and the relationship to the signal references in ADIv5.1. The interface does not include a return clock signal. RTCK and the nTRST signals are optional because this only relates to resetting the DBGTAP state machine which can be performed by transmitting 5 TCK pulses with TMS HIGH.

Table 2.1. JTAG-DP physical interface

Implementation signal name (JTAG-DP)ADIv5.1 signal name (JTAG-DP)TypeJTAG-DP signal description
TDIDBGTDIInputDebug Data In
TDODBGTDOOutputDebug Data Out
SWCLKTCKTCKInputDebug Clock
SWDITMSDBGTMSInputDebug Mode Select
nTRSTDBGTRSTnInputDebug TAP Reset

Programmers model

Table 2.2 lists all implemented registers accessible by JTAG-DP. All other IR instructions are implemented as BYPASS and an external TAP controller must be implemented in accordance with ADIv5.1 if more IR registers are required, for example JTAG TAP boundary scan.

Table 2.2. JTAG-DP registers

IR instruction valueJTAG-DP registerDR scan widthDescription
b1000ABORT35JTAG-DP Abort Register (ABORT)
b1010DPACC35JTAG DP/AP Access Registers (DPACC/APACC)
b1011APACC35
b1110IDCODE32JTAG Device ID Code Register (IDCODE)
b1111BYPASS1JTAG Bypass Register (BYPASS)

For more information about these registers, their features, and how to access them, see the ARM Debug Interface v5 Architecture Specification and the ARM Debug Interface v5.1 Architecture Supplement. Implementation specific detail is described in Common debug port features and registers.

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