2.5.4. Implementation specific registers

This section describes the implementation specific registers.

AP Abort Register, ABORT

The AP Abort Register is always present on all debug port implementations. It forces a DAP abort and, on a SW-DP, it is also used to clear error and sticky flag conditions.

JTAG-DP

It is at address 0x0 when the Instruction Register (IR) contains ABORT.

SW-DP

It is at address 0x0 on write operations when the APnDP bit = 0. Access to the AP Abort Register is not affected by the value of the CTRLSEL bit in the Select Register.

The AP Abort Register is:

  • a write-only register.

  • always accessible, and returns an OK response if a valid transaction is received.

Accesses to this register always complete on the first attempt.

Figure 2.12 shows the AP Abort Register bit assignments.

Figure 2.12. AP Abort Register bit assignments


Table 2.7 shows the AP Abort Register bit assignments.

Table 2.7. AP Abort Register bit assignments

BitsFunctionDescription
[31:5]-Reserved, SBZ.
[4]ORUNERRCLR[a]Write 1 to this bit to clear the STICKYORUN overrun error flag[b] to 0.
[3]WDERRCLR[a]Write 1 to this bit to clear the WDATAERR write data error flag[b] to 0.
[2]STKERRCLR[a]Write 1 to this bit to clear the STICKYERR sticky error flag[b] to 0.
[1]STKCMPCLR[a]Write 1 to this bit to clear the STICKYCMP sticky compare flag[b] to 0.
[0]DAPABORT

Write 1 to this bit to generate a DAP abort. This aborts the current AP transaction.

Do this only if the debugger has received WAIT responses over an extended period.

[a] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, SBZ.

[b] In the Control/Status Register, see Control/Status Register, CTRL/STAT.


Identification Code Register, IDCODE

The Identification Code Register is always present on all debug port implementations. It provides identification information about the ARM Debug Interface.

JTAG-DP is accessed using its own scan chain.

SW-DP is at address 0b00 on read operations when the APnDP bit = 0. Access to the Identification Code Register is not affected by the value of the CTRLSEL bit in the Select Register. The Identification Code Register is:

  • a read-only register

  • always accessible.

Figure 2.13 shows the Identification Code Register bit assignments.

Figure 2.13. Identification Code Register bit assignments


Table 2.8 shows the Identification Code Register bit assignments.

Table 2.8. Identification Code Register bit assignments

BitsFunctionDescription
[31:28]Version

Version code:

JTAG-DP

0x4

SW-DP

0x3

[27:12]PARTNO

Part Number for the debug port. This value is provided by the designer of the Debug Port and must not be changed. Current ARM-designed debug ports have the following PARTNO values:

JTAG-DP

0xBA00

SW-DP

0xBA02

[11:1]MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the designer of the device. See JEDEC Manufacturer ID. The ARM value for this field, shown in Figure 2.13, is 0x23B. This value must not be changed.

[0]-Always 0b1.

JEDEC Manufacturer ID

This code is also described as the JEP-106 manufacturer identification code, and can be subdivided into two fields, as shown in Table 2.9. JDEC codes are assigned by the JEDEC Solid State Technology Association, see JEP106M, Standard Manufacture's Identification Code.

Table 2.9. JEDEC JEP-106 manufacturer ID code, with ARM values

JEP-106 fieldBits[a]ARM registered value
Continuation code4 bits, [11:8]b0100, 0x4
Identity code7 bits, [7:1]b0111011, 0x3B

[a] Field width, in bits, and the corresponding bits in the Identification Code Register.


Control/Status Register, CTRL/STAT

The Control/Status Register is always present on all debug port implementations. It provides control of the debug port, and status information about the debug port. JTAG-DP It is at address 0x4 when the Instruction Register (IR) contains DPACC. SW-DP is at address 0b01 on read and write operations when the APnDP bit = 0 and the CTRLSEL bit in the Select Register is set to b0. For information about the CTRLSEL bit see AP Select Register, SELECT.

The Control/Status Register is a read-write register, in which some bits have different access rights. It is Implementation-defined whether some fields in the register are supported. Figure 2.14 shows the Control/Status Register bit assignments.

Figure 2.14. Control/Status Register bit assignments


Table 2.10 shows the Control/Status Register bit assignments.

Table 2.10. Control/Status Register bit assignments

BitsAccessFunctionDescription
[31]ROCSYSPWRUPACKSystem power-up acknowledge.
[30]R/WCSYSPWRUPREQ

System power-up request.

After a reset this bit is LOW (0).

[29]ROCDBGPWRUPACKDebug power-up acknowledge.
[28]R/WCDBGPWRUPREQ

Debug power-up request.

After a reset this bit is LOW (0).

[27]ROCDBGRSTACKDebug reset acknowledge.
[26]R/WCDBGRSTREQ

Debug reset request.

After a reset this bit is LOW (0).

[25:24]--Reserved, RAZ/SBZP
[23:12]R/WTRNCNT

Transaction counter.

After a reset the value of this field is Unpredictable.

[11:8]R/WMASKLANE

Indicates the bytes to be masked in pushed compare and pushed verify operations.

After a reset the value of this field is Unpredictable.

[7]ROaWDATAERR[a]

This bit is set to 1 if a Write Data Error occurs. It is set if:

  • there is a a parity or framing error on the data phase of a write

  • a write that has been accepted by the debug port is then discarded without being submitted to the access port.

This bit can only be cleared by writing b1 to the WDERRCLR field of the Abort Register.

After a power-on reset this bit is LOW (0).

[6]ROaREADOKa

This bit is set to 1 if the response to a previous access port or RDBUFF was OK. It is cleared to 0 if the response was not OK.

This flag always indicates the response to the last access port read access.

After a power-on reset this bit is LOW (0).

[5]RO[b]STICKYERR

This bit is set to 1 if an error is returned by an access port transaction. To clear this bit:

JTAG-DP

Write b1 to this bit of this register.

SW-DP

Write b1 to the STKERRCLR field of the Abort Register.

After a power-on reset this bit is LOW (0).

[4]ROaSTICKYCMP

This bit is set to 1 when a match occurs on a pushed compare or a pushed verify operation. To clear this bit:

JTAG-DP

Write b1 to this bit of this register.

SW-DP

Write b1 to the STKCMPCLR field of the Abort Register.

After a power-on reset this bit is LOW (0).

[3:2]R/WTRNMODE

This field sets the transfer mode for access port operations.

After a power-on reset the value of this field is Unpredictable.

[1]ROaSTICKYORUN

If overrun detection is enabled (see bit [0] of this register), this bit is set to 1 when an overrun occurs. To clear this bit:

JTAG-DP

Write b1 to this bit of this register.

SW-DP

Write b1 to the ORUNERRCLR field of the Abort Register.

After a power-on reset this bit is LOW (0).

[0]R/WORUNDETECT

This bit is set to b1 to enable overrun detection.

After a reset this bit is LOW (0).

[a] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, RAZ/SBZP.

[b] RO on SW-DP. On a JTAG-DP, this bit can be read normally, and writing b1 to this bit clears the bit to b0.


AP Select Register, SELECT

The AP Select Register is always present on all debug port implementations. Its main purpose is to select the current access port and the active four-word register window in that access port. On a SW-DP, it also selects the debug port address bank.

JTAG-DP

It is at address 0x8 when the Instruction Register (IR) contains DPACC, and is a read/write register.

SW-DP

It is at address 0b10 on write operations when the APnDP bit = 0, and is a write-only register. Access to the AP Select Register is not affected by the value of the CTRLSEL bit.

Figure 2.15 shows the AP Select Register bit assignments.

Figure 2.15. AP Select Register bit assignments


Table 2.11 shows the AP Select Register bit assignments.

Table 2.11. AP Select Register bit assignments

BitsFunctionDescription
[31:24]APSEL

Selects the current access port.

0x00 - AHB-AP

0x01 - APB-AP

0x02 - JTAG-AP

0x03 - Cortex-M3 if present.

The reset value of this field is Unpredictable.[a]

[23:8]-Reserved. SBZ/RAZa.
[7:4]APBANKSEL

Selects the active four-word register window on the current access port.

The reset value of this field is Unpredictable.a

[3:0]DPBANKSEL[b]

Selects the register that appears at DP register 0x4:

0x0 - CTRL/STAT, read/write

0x1 - DLCR, read/write

0x2 - TARGETID, read-only

0x3 - DLPIDR, read-only.

All other values are reserved. Writing a reserved value to this field is Unpredictable.

[a] On a SW-DP the register is write-only, therefore you cannot read the field value.

[b] SW-DP only. On a JTAG-DP this bit is Reserved, SBZ/RAZ.


If APSEL is set to a non-existent access port, all access port transactions return zero on reads and are ignored on writes.

Note

Every ARM Debug Interface implementation must include at least one access port.

Read Buffer, RDBUFF

The 32-bit Read Buffer is always present on all debug port implementations. However, there are significant differences in its implementation on JTAG and SW Debug Ports.

JTAG-DP

It is at address 0xC when the Instruction Register (IR) contains DPACC, and is a Read-as-zero, Writes ignored (RAZ/WI) register.

SW-DP

It is at address 0b11 on read operations when the APnDP bit = 0 and is a read-only register. Access to the Read Buffer is not affected by the value of the CTRLSEL bit in the SELECT Register.

Read Buffer implementation and use on a JTAG-DP

On a JTAG-DP, the Read Buffer always reads as zero, and writes to the Read Buffer address are ignored.

The Read Buffer is architecturally defined to provide a debug port read operation that does not have any side effects. This means that a debugger can insert a debug port read of the Read Buffer at the end of a sequence of operations, to return the final Read Result and ACK values.

Read Buffer implementation and use on a SW-DP

On a SW-DP, performing a read of the Read Buffer captures data from the access port, presented as the result of a previous read, without initiating a new access port transaction. This means that reading the Read Buffer returns the result of the last access port read access, without generating a new AP access.

After you have read the Read Buffer, its contents are no longer valid. The result of a second read of the Read Buffer is Unpredictable.

If you require the value from an access port register read, that read must be followed by one of:

  • A second access port register read. You can read the Control/Status Register (CSW) if you want to ensure that this second read has no side effects.

  • A read of the DP Read Buffer.

This second access, to the access port or the debug port depending on which option you used, stalls until the result of the original access port read is available.

Wire Control Register, WCR (SW-DP only)

The Wire Control Register is always present on any SW-DP implementation. Its purpose is to select the operating mode of the physical serial port connection to the SW-DP.

It is a read/write register at address 0b01 on read and write operations when the CTRLSEL bit in the Select Register is set to b1. For information about the CTRLSEL bit see AP Select Register, SELECT.

Note

When the CTRLSEL bit is set to b1, to enable access to the WCR, the DP Control/Status Register is not accessible.

Many features of the Wire Control Register are implementation-defined.

Figure 2.16 shows the Wire Control Register bit assignments.

Figure 2.16. Wire Control Register bit assignments


Table 2.12 shows the Wire Control Register bit assignments.

Table 2.12. Wire Control Register bit assignments

BitsFunctionDescription
[31:10]-Reserved. SBZ/RAZ.
[9:8]TURNROUND

Turnaround tristate period, see Turnaround tristate period, TURNROUND, bits [9:8].

After a reset this field is b00.

[7:6]WIREMODE

Identifies the operating mode for the wire connection to the debug port, see Wire operating mode, WIREMODE, bits [7:6].

After a reset this field is b01.

[5:3]-Reserved. SBZ/RAZ.
[2:0]PRESCALERReserved. SBZ/RAZ.

Turnaround tristate period, TURNROUND, bits [9:8]

This field defines the turnaround tristate period. This turnaround period allows for pad delays when using a high sample clock frequency. Table 2.13 lists the allowed values of this field, and their meanings.

Table 2.13. Turnaround tristate period field bit definitions

TURNROUND[a]Turnaround tri-state period
b001 sample period
b012 sample periods
b103 sample periods
b114 sample periods

[a] Bits [9:8] of the WCR Register.


Wire operating mode, WIREMODE, bits [7:6]

This field identifies SW-DP as operating in Synchronous mode only. This field is required, and Table 2.14 lists the allowed values of the field, and their meanings.

Table 2.14. Wire operating mode bit definitions

WIREMODE[a]Wire operating mode
b00Reserved
b01Synchronous (no oversampling)
b1XReserved

[a] Bits [7:6] of the WCR Register.


Target Identification Register, TARGETID (SW-DP only)

The Target Identification Register provides information about the target when the host is connected to a single device. The Target Identification Register is:

  • a read-only register

  • accessed by a read of DP register 0x4 when the DPBANKSEL bit in the SELECT Register is set to 0x2.

The value of this register reflects the value of the TARGETID[31:0] input.

Figure 2.17 shows the Target Identification Register bit assignments.

Figure 2.17. Target Identification Register bit assignments


Table 2.15 shows the Target Identification Register bit assignments.

Table 2.15. Target Identification Register bit assignments

BitsFunctionDescription
[31:28]TREVISIONTarget revision.
[27:12]TPARTNOImplementation defined. This value is assigned by the designer of the part and must be unique to that part.
[11:1]TDESIGNERImplementation defined. This field identifies the designer of the part. The value is based on the code assigned to the designer by JEDEC standard JEP-106, as used in IEEE 1149.1.
[0]-Reserved, RAO.

Data Link Protocol Identification Register, DLPIDR (SW-DP only)

The Data Link Protocol Identification Register provides information about the Serial Wire protocol version. The Data Link Protocol Identification Register is:

  • a read-only register

  • accessed by a read of DP register 0x4 when the DPBANKSEL bit in the SELECT Register is set to 0x3.

The contents of this register are data link defined.

Figure 2.18 shows the Data Link Protocol Identification Register bit assignments.

Figure 2.18. Data Link Protocol Identification Register bit assignments


Table 2.16 shows the Data Link Protocol Identification Register bit assignments.

Table 2.16. Data Link Protocol Identification Register bit assignments

BitsFunctionDescription
[31:28]Target Instance

Implementation defined. This field defines a unique instance number for this device within the system. This value must be unique for all devices that are connected together in a multi-drop system with identical values in the TREVISION fields in the TARGETID Register. The value of this field reflects the value of the INSTANCEID[3:0] input.

[27:4]-Reserved.
[3:0]Protocol Version

Defines the Serial Wire protocol version. This value is 0x1, which indicates SW protocol version 2.


Read Resend Register, RESEND (SW-DP only)

The Read Resend Register is always present on any SW-DP implementation. It enables the read data to be recovered from a corrupted debugger transfer, without repeating the original AP transfer.

It is a 32-bit read-only register at address 0b10 on read operations. Access to the Read Resend Register is not affected by the value of the DPBANKSEL bit in the SELECT Register.

Performing a read to the RESEND register does not capture new data from the access port. It returns the value that was returned by the last AP read or DP RDBUFF read.

Reading the RESEND register enables the read data to be recovered from a corrupted transfer without having to re-issue the original read request or generate a new DAP or system level access.

The RESEND register can be accessed multiple times. It always returns the same value until a new access is made to the DP RDBUFF register or to an access port register.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential