4.4.6. CTI Trigger to Channel Enable Registers, CTIINEN0-7, 0x020-0x03C

The CTI Trigger to Channel Enable Registers enable the signalling of an event on CTM channels when the core issues a trigger, CTITRIGIN, to the CTI. There is one register for each of the eight CTITRIGIN inputs. Within each register there is one bit for each of the four channels implemented. These registers do not affect the application trigger operations.

Figure 4.8 shows the bit assignments.

Figure 4.8. CTI Trigger to Channel Enable Registers bit assignments


Table 4.7 shows the bit assignments.

Table 4.7. CTI Trigger to Channel Enable Registers bit assignments

BitsNameDescription
[31:4]-Reserved RAZ DNM.
[3:0]TRIGINEN

Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.

1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.

There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.

0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.


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