12.7.1. Control Register, CR, 0xE80

This is the control word used to configure and control transfers through the APB interface.

Figure 12.7 shows the Control Register bit assignments.

Figure 12.7. Control Register bit assignments


Table 12.8 shows the Control Register bit assignments.

Table 12.8. Control Register bit assignments

BitsNameDescription
[31:24]-Reserved RAZ/SBZP
[23]ITMBusyITM is transmitting trace and FIFO is not empty
[22:16]TraceIDATIDM[6:0] value
[15:10]-Reserved RAZ/SBZP
[9:8]TSPrescale[a]Timestamp Prescaler, 0b00=/1, 0b01=/4, 0b10=/16, 0b11=/64
[7:4]-Reserved RAZ/SBZP
[3]DWTEn[b]Enable DWT input port
[2]SYNCEn[c]Enable sync packets
[1]TSSEnEnable timestamps, delta
[0]ITMEn[d]

Enable ITM stimulus, also acts as a global enable

[a] The TSPrescale bit is reset to 0x0. This means that the timestamp counts on every ATCLK tick. However, you can program the TSPrescale bit so that the timestamp counts once every 4, 16, or 64 ATCLK ticks.

[b] Data Watchpoint and Trace (DWT) is not used in the CoreSight ITM, so the DWTEn bit is always 0x0.

[c] The SYNCEn bit is always 0x1 and is enabled.

[d] It is recommended that the ITMEn bit is cleared and waits for the ITMBusy bit to be cleared, before changing any fields in the Control Register, otherwise the behavior can be unpredictable. See Overflow packet for information about disabling the ITM overflow packets.


Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential