9.4. ETB CoreSight management registers

This section gives information specific to the ETB programmable registers.

Claim tags, 0xFA0 and 0xFA4

The ETB implements a four-bit claim tag. The use of bits [3:0] is software defined.

Lock access mechanism, 0xFB0 and 0xFB4

The ETB implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked.

Authentication Status, 0xFB8 [7:0]

Reports the required security level. This is set to 0x00 for functionality not implemented.

Device ID, 0xFC8

The ETB has the default value 0x00.

Table 9.22 shows the Device ID bit assignments.

Table 9.22. CSTF Device ID bit assignments

BitsValueDescription
[31:6]0x0000000Reserved.
[5]1’b0Indicates that the ETB RAM operates synchronously to ATCLK.
[4:0]5’b0000

Hidden Level of Input multiplexing.

When non-zero this value indicates the type/number of ATB multiplexing present on the input to the ATB.

Currently only 0x00 is supported (no multiplexing present). This value is used to assist topology detection of the ATB structure.


Device Type Identifier, 0xFCC [7:0]

0x21 indicates this device is a trace sink and specifically an ETB.

PartNumber, 0xFE4 [3:0], 0xFE0 [7:4], 0xFE0 [3:0]

Upper, middle, and lower BCD value of Device number. Set to 0x907.

Designer JEP106 value, 0xFD0[3:0], 0xFE8[2:0], 0xFE4[7:4]

The ETB is identified as an ARM component with a JEP106 identity at 0x3B and a JEP106 continuation code at 0x4 (fifth bank).

Component class, 0xFF4[7:4]

The ETB complies to the CoreSight class of components and this value is set to 0x9.

See Table 1.1 for the current value of the revision field at offset 0xFE8[7:4].

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