12.6.2. Trace Trigger Register, TTR, 0xE20

Each bit in the register represents one of the virtual stimulus registers. When the bit is set, a pulse is sent on TRIGOUT when writing to the corresponding Stimulus Register. The pulse is held until TRIGOUTACK is returned, which can result in masking of multiple triggers with one acknowledgement. Triggers are not generated if trace is disabled. When secure non-invasive debug, or secure trace, is disabled, no triggers are generated for Stimulus Registers 16 to 31. If non-secure non-invasive debug, or trace, is disabled, no triggers are generated. The register is zero on reset, and the default is no triggers generated.

Table 12.7 shows the Trace Trigger Register bit assignments.

Table 12.7. Trace Trigger Register bit assignments

BitsNameDescription
[31:0]Trigger MaskBit mask to enable trigger generation, TRIGOUT, on selected writes to the Stimulus Registers

Figure 12.6 shows two writes to the stimulus port. It shows the timing for generating TRIGOUT and deasserting TRIGOUT with TRIGOUTACK. PENABLE and PREADY show when a write happens to the Stimulus Register.

Figure 12.6. TRIGOUT and TRIGOUTACK operation


The write at T0-T2 causes the TRIGOUT. This is acknowledged at T5. A write at T2-T4 generates another TRIGOUT. If the TRIGOUTACK stays HIGH beyond T6, this TRIGOUT is also acknowledged at T6. In the example TRIGOUTACK goes LOW before T6, so another TRIGOUTACK is required.

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