11.10.3. Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8

Figure 11.8 shows the Integration Test ATB Control Register 0 bit assignments.

Figure 11.8. Integration Test ATB Control Register 0 bit assignments


Table 11.10 shows the Integration Test ATB Control Register 0 bit assignments.

Table 11.10. Integration Test ATB Control Register 0 bit assignments

BitsNameDescription
[31:1]-Reserved RAZ/SBZP.
[0]ATVALIDReads the value of ATVALIDS. Topology detection register, always present.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential