A.8. CoreSight ETB signals

Table A.8 shows the CoreSight Embedded Trace Bus (ETB) signals.

Table A.8. CoreSight ETB signals

NameTypeDescriptionClock domain
AFREADYSInputATB Data flush complete for the master portATCLK
ATBYTESS[1:0]InputATB Number of valid bytes, LSB aligned, on the slave portATCLK
ATCLKInputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAS[31:0]InputATB Trace data on the slave portATCLK
ATIDS[6:0]InputATB ID for current trace data on slave portATCLK
ATRESETnInputATB Reset for the ATCLK domainATCLK
ATVALIDSInputATB Valid signals present on slave portATCLK
FLUSHINInputFlush input from the CTIATCLK/None
MBISTADDR[CSETB_RAM_ADRW-1:0]InputMemory BIST addressATCLK
MBISTCEInputMemory BIST chip enableATCLK
MBISTDIN[31:0]InputMemory BIST data inATCLK
MBISTWEInputMemory BIST write enableATCLK
MTESTONInputMemory BIST test is enabledATCLK
PADDRDBG[11:2]InputDebug APB address busPCLKDBG
PADDRDBG31 InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBGInputDebug APB clockN/A
PCLKENDBGInputDebug APB clock enablePCLKDBG
PENABLEDBGInputDebug APB enable signal, indicates second and subsequent cyclesPCLKDBG
PRESETDBGnInputDebug APB resetPCLKDBG
PSELDBGInputDebug APB component selectPCLKDBG
PWDATADBG[31:0]InputDebug APB write data busPCLKDBG
PWRITEDBGInputDebug APB write transferPCLKDBG
SEInputScan Enable 
TRIGINInputTrigger input from the CTIATCLK/None
ACQCOMPOutputTrace acquisition completeATCLK
AFVALIDSOutputATB Data flush request for the master portATCLK
ATREADYSOutputATB transfer ready on slave portATCLK
FLUSHINACK OutputFlush input acknowledgementATCLK
FULLOutputCSETB RAM overflow or wrapped around ATCLK
MBISTDOUT[31:0]OutputMemory BIST data outATCLK
PRDATADBG[31:0]OutputDebug APB read data busPCLKDBG
PREADYDBGOutputDebug APB Ready signalPCLKDBG
TRIGINACKOutputTrigger input acknowledgementATCLK

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